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| toshiba original cmos 32-bit microcontroller tlcs-900/h1 series TMP92CD54IFG tentative semiconductor company
preface thank you very much for making us e of toshiba microcomputer lsis. before use this lsi, refer the section, ?points of note and restrictions?. tmp92cd54i 2009-12-26 92cd54i-1 tentative cmos 32-bit micro-controller TMP92CD54IFG 1. outline and device characteristics the tmp92cd54i is a high-performance 32-b it microcontroller incorporating a toshiba- proprietary cpu, the tlcs-900/h1 core. the tmp 92cd54i is deve loped for various automotive equipments which require high-speed data processing. housed in a 100-pin mini-flat package, the tm p92cd54i is best suited for high-density implementation of user systems. the characteristics of the tmp92cd54i are listed below: (1) toshiba-proprietary high-speed 32-bit cpu (tlcs-900/h1 cpu) fully-compatible with the instruction codes of the tlcs-900, tlcs-900/l, elcs-900/l1, tlcs-900/h and tlcs-900/h2 16 mbytes of linear address space general-purpose registers and register banks micro dma: 8 channels (250 ns/4 bytes at fc = 20 mhz) minimum instruction execution time: 50 ns (at fc = 20 mhz) internal data bus: 32-bit wide (2) internal memory internal ram : 32k-byte (32 bit/one clock ac cess time, can be used for instructions. internal rom : 512k-byte mask rom (3) external memory expansion expandable up to 16-mbyte (for code and data) external data bus: 8-bit wide (the upper addr ess bus is not available when the built-in i/os are selected.) (4) memory controller (memc) chip select output: 1 channel (5) 8-bit timer : 8 channels 8-bit interval timer mode (8 channels) 16-bit interval timer mode (4 channels) 8-bit programmable pulse generation (ppg) output mode (4 channels) 8-bit pulse width modulation (pwm) output mode (4 channels) (6) 16-bit timer : 2 channels 16-bit interval timer mode (2 channels) 16-bit event counter mode (2 channels) 16-bit programmable pulse generation (ppg) output mode (2 channels) frequency measurement mode pulse width measurement mode time difference measurement mode (7) serial interface (sio) : 2 channels i/o interface mode universal asynchronous receiver transmitter (uart) mode (8) serial expansion interface (sei) : 1 channel baud rate 4m / 2m / 500kbps at fc = 20mhz. (9) serial bus interface (sbi) : 3 channels clock-synchronous 8-bit serial interface mode i 2 c bus mode tmp92cd54i 2009-12-26 92cd54i-2 tentative (10) can controller : 1 channel supports can version 2.0b. 16 mailboxes (11) 10-bit a/d converter (adc) : 12 channels a/d conversion time: 8 sec (at fc = 20 mhz) total tolerance: 3 lsb (excluding quantization error) scan mode for all 12 channels (12) watch dog timer (wdt) (13) timer for real-time clock (rtc) can operate with low-frequency oscillator only. (14) interrupt controller (intc) : 60 interrupt sources 9 interrupts from cpu (software interrupts and undefined instruction interrupt) 42 internal interrupt vectors 9 external interrupt vectors (int0 to int7, nmi ) (15) i/o port : 68 pins (16) standby mode four modes: idle3, idle2, idle1 and stop stop mode can be released by 9 external inputs. (17) internal voltage detection flag (ramstb) (18) power supply voltage v cc5 = 4.5 v to 5.25 v v cc3 = 3.3 v (connect regout (built-in vo ltage regulator output) to dvcc3.) (19) operating temperature : -40 to 85 degree c (20) package : lqfp100-p-1414-0.50f tmp92cd54i 2009-12-26 92cd54i-3 tentative figure 1.1 tmp92cd54i block diagram pm0( ss /a8) pm1(mosi/a9) pm2(miso/a10) pm3(seclk/a11) pn0(sck0) pn1(so0/sda0) pn2(si0/scl0) pn3(sck1/a12) pn4(so1/sda1/a13) pn5(si1/scl1/a14) p00 to p07(d0 to d7) p40 to p47(a0 to a7) p70( rd ) p71( wr ) p73( cs ) p74 p75( wait ) dvss [6] dvcc5 [5] regen dvcc3 [3] connect port 0 port 4 interrupt controller serial bus i/f channel 0 serial bus i/f channel 1 serial exp. i/f int0 port 7 32kb ram 512kb mask rom serial i/o channel 0 serial i/o channel 1 10-bit 12ch a/d converter 32 bits xsp xiz xiy xix xhl xde xbc xwa ix iy iz sp l h e d c b a w f sr p c 900/h1 cpu watch-dog timer real time clock (rtc) (to7/int4)pc5 8-bit timer (timer0) 8-bit timer (timer1) 8-bit timer (timer2) 8-bit timer (timer3) 8-bit timer (timer4) 8-bit timer (timer5) 8-bit timer (timer6) 8-bit timer (timer7) (ti4/int3)pc3 (to3/int2)pc2 (to5)pc4 (ti0/int1)pc0 (to1)pc1 can controller (tx)pf6 (rx)pf7 vrefl vrefh advss advcc pg0 to pg7 (an0 to an7) pl0 to pl3 (an8 to an11) regout xt1 xt2 x1 x2 serial bus i/f channel 2 pm4(sck2) pn6(so2/sda2/a15) p72(si2/scl2) nmi a m0 a m1 test0 test1 reset (sclk0/ cts0 )pf2 (rxd0)pf1 (txd0)pf0 (sclk1/ cts1 )pf5 (rxd1)pf4 (txd1)pf3 (ti9/wuint1/int6/a17)pd1 (ti8/wuint0/int5/a16)pd0 (to8/wuint2/a18)pd2 (to9/wuint3/a19)pd3 (tia/wuint4/int7/a20)pd4 (tib/wuint5/a21)pd5 (toa/wuint6/a22)pd6 (tob/wuint7/a23)pd7 16-bit timer (timer8) 16-bit timer (timera) osc rtc regulator clk tmp92cd54i 2009-12-26 92cd54i-4 tentative 2. pin assignment and functions 2.1 pin assignment figure 2.1 tmp92cd54i pin assignment dvcc5 x1 dvss x2 test1 xt1 xt2 dvcc3 pn6/so2/sda2/a15 pn5/si1/scl1/a14 pn4/so1/sda1/a13 pn3/sck1/a12 dvss pn2/si0/scl0 dvcc5 pn1/so0/sda0 pn0/sck0 pc0/ti0/int1 pc1/to1 pc2/to3/int2 pc3/ti4/int3 pc4/to5 pc5/to7/int4 regen dvss pl3/an11 pl2/an10 pl1/an9 pl0/an8 pg7/an7 pg6/an6 pg5/an5 pg4/an4 pg3/an3 pg2/an2 pg1/an1 pg0/an0 dvss p75/wait dvcc3 p74 p73/cs p72/si2/scl2 p71/wr p70/rd am0 reset am1 clk test0 TMP92CD54IFG (lqfp100-p-1414-0.50f) 14 14 1.4 top view 01 05 10 15 20 25 75 70 65 60 55 51 50 45 40 35 30 26 076 080 085 090 095 d6/p06 d7/p07 a0/p40 a1/p41 a2/p42 a3/p43 a4/p44 a5/p45 a6/p46 a7/p47 dvcc3 int0 dvss nmi dvcc5 a16/wuint0/int5/ti8/pd0 a17/wuint1/int6/ti9/pd1 a18/wuint2/to8/pd2 a19/wuint3/to9/pd3 a20/wuint4/int7/tia/pd4 a21/wuint5/tib/pd5 a22/wuint6/toa/pd6 a23/wuint7/tob/pd7 regout dvcc5 100 advss advcc vrefl vrefh rx/pf7 tx/pf6 cts1/sclk1/pf5 rxd1/pf4 txd1/pf3 cts0/sclk0/pf2 rxd0/pf1 txd0/pf0 dvss pm4/sck2 dvcc5 a8/ss/pm0 a9/mosi/pm1 a10/miso/pm2 a11/seclk/pm3 d0/p00 d1/p01 d2/p02 d3/p03 d4/p04 d5/p05 tmp92cd54i 2009-12-26 92cd54i-5 tentative 2.2 pin names and functions the names and functions of the input/output pins are described in are described in the tables 2.2.1 to 2.2.4. table 2.2.1 input/output pins (1/4) pin name pin number number of pins in/out function (cmos) p00 to p07 d0 to d7 20 to 27 8 (ttl) in/out in/out port 0: i/o port. input or output specifiable in units of bits. data: data bus 0 to 7. p40 to p47 a0 to a7 28 to 35 8 in/out out port4: i/o port. input or output specifiable in units of bits. address: address bus 0 to 7. p70 rd 81 1 in/out out port70: i/o port. read: outputs strobe signal to read external memory. p71 wr 82 1 in/out out port 71: i/o port. write: output strobe signal to write external memory. p72 si2 scl2 83 1 in/out port 72: i/o port. sbi channel 2: input data at sio mode sbi channel 2: clock input/output at i2c mode p73 cs 84 1 in/out out port 73: i/o port. chip select: outputs ?low? if address is within specified address area. p74 85 1 in/out port 74: i/o port. p75 wait 87 1 in/out in port 75: i/o port. wait: signal used to request cpu bus wait. pc0 ti0 int1 58 1 in/out in in port c0: i/o port. timer input 0: input pin for timer 0. interrupt request pin 1: rising-edge interrupt request pin. pc1 to1 57 1 in/out out port c1: i/o port. timer output 1: output pin for timer 1. pc2 to3 int2 56 1 in/out out in port c2: i/o port. timer output 3: output pin for timer 3. interrupt request pin 2: rising-edge interrupt request pin. pc3 ti4 int3 55 1 in/out in in port c3: i/o port. timer input 4: input pin for timer 4. interrupt request pin 3: rising-edge interrupt request pin. pc4 to5 54 1 in/out out port c4: i/o port. timer output 5: output pin for timer 5. pc5 to7 int4 53 1 in/out out in port c5: i/o port. timer output 7: output pin for timer 7. interrupt request pin 4: rising-edge interrupt request pin. pd0 ti8 int5 a16 wuint0 41 1 in/out in in out in port d0: i/o port. timer input 8: input pin for timer 8. interrupt request pin 5: interrupt reques t pin with programmable rising/falling edge. address: address bus 16. wake up input 0: wake up request pin with programmable rising, falling or both falling and rising edge. pd1 ti9 int6 a17 wuint1 42 1 in/out in in out in port d1: i/o port. timer input 9: input pin for timer 9. interrupt request pin 6: rising-edge interrupt request pin. address: address bus 17. wake up input 1: wake up request pin with programmable rising, falling or both falling and rising edge. pd2 to8 a18 wuint2 43 1 in/out out out in port d2: i/o port. timer output 8: output pin for timer 8 address: address bus 18. wake up input 2: wake up request pin with programmable rising, falling or both falling and rising edge. wuint2 wuint0 wuint1 int6 int1 int2 int3 int4 int5 tmp92cd54i 2009-12-26 92cd54i-6 tentative table 2.2.2 input/output pins (2/4) pin name pin number number of pins in/out function pd3 to9 a19 wuint3 44 1 in/out out out in port d3: i/o port. timer output 9: output pin for timer 9 address: address bus 19. wake up input 3: wake up request pin with programmable rising, falling or both falling and rising edge. pd4 tia int7 a20 wuint4 45 1 in/out in in out in port d4: i/o port. timer input a: input pin for timer a interrupt request pin 7: interrupt request pin with programmable rising/falling edge. address: address bus 20. wake up input 4: wake up request pin with programmable rising, falling or both falling and rising edge. pd5 tib a21 wuint5 46 1 in/out in out in port d5: i/o port. timer input b: input pin for timer b. address: address bus 21. wake up input 5: wake up request pin with programmable rising, falling or both falling and rising edge. pd6 toa a22 wuint6 47 1 in/out out out in port d6: i/o port. timer output a: output pin for timer a. address: address bus 22. wake up input 6: wake up request pin with programmable rising, falling or both falling and rising edge. pd7 tob a23 wuint7 48 1 in/out out out in port d7: i/o port. timer output b: output pin for timer b. address: address bus 23. wake up input 7: wake up request pin with programmable rising, falling or both falling and rising edge. pf0 txd0 12 1 in/out out port f0: i/o port. serial interface channel 0: transmission data. pf1 rxd0 11 1 in/out in port f1: i/o port. serial interface channel 0: receive data. pf2 sclk0 cts0 10 1 in/out in/out in port f2: i/o port. serial interface channel 0: clock input/output. serial interface channel 0: data ready to send. (clear-to-send) pf3 txd1 9 1 in/out out port f3: i/o port. serial interface channel 1: transmission data. pf4 rxd1 8 1 in/out in port f4: i/o port. serial interface channel 1: receive data. pf5 sclk1 cts1 7 1 in/out in/out in port f5: i/o port. serial interface channel 1: clock input/output. serial interface channel 1: data ready to send. (clear-to-send) pf6 tx 6 1 in/out out port f6: i/o port. can: transmission data. pf7 rx 5 1 in/out in port f7: i/o port. can: receive data. pg0 to pg7 an0 to an7 89 to 96 8 in in port g: input-only port. analog input 0 to 7: ad converter input pins. pl0 to pl3 an8 to an11 97 to 100 4 in in port l0 to l3: input-only port. analog input 8 to 11: ad converter input pins. pm0 ss a8 16 1 in/out in out port m0: i/o port. sei: slave select input. address: address bus 8. pm1 mosi a9 17 1 in/out in/out out port m1: i/o port. sei: master output, slave input. address: address bus 9. wuint7 wuint6 wuint5 wuint4 int7 wuint3 tmp92cd54i 2009-12-26 92cd54i-7 tentative table 2.2.3 input/output pins (3/4) pin name pin number number of pins in/out function pm2 miso a10 18 1 in/out in/out out port m2: i/o port. sei: master input, slave output. address: address bus 10. pm3 seclk a11 19 1 in/out in/out out port m3: i/o port. sei: clock input/output. address: address bus 11. pm4 sck2 14 1 in/out in/out port m4: i/o port. sbi channel 2: clock input/output at sio mode. pn0 sck0 59 1 in/out in/out port n0: i/o port. sbi channel 0: clock input/output at sio mode. pn1 so0 sda0 60 1 in/out out in/out port n1: i/o port. sbi channel 0: output data input/output at sio mode sbi channel 0: data input/output at i2c mode pn2 si0 scl0 62 1 in/out in in/out port n2: i/o port. sbi channel 0: input data at sio mode sbi channel 0: clock input/output at i2c mode pn3 sck1 a12 64 1 in/out in/out out port n3: i/o port. sbi channel 1: clock input/output at sio mode address: address bus 12. pn4 so1 sda1 a13 65 1 in/out out in/out out port n4: i/o port. sbi channel 1: output data at sio mode sbi channel 1: data input/output at i2c mode address: address bus 13. pn5 si1 scl1 a14 66 1 in/out in in/out out port n5: i/o port. sbi channel 1: input data at sio mode sbi channel 1: clock input/output at i2c mode address: address bus 14 pn6 so2 sda2 a15 67 1 in/out out port n6: i/o port. sbi channel 2: output data at sio mode sbi channel 2: data input output at i2c mode address: address bus 15. nmi 39 1 in non-maskable interrupt: interrupt request pin with programmable falling or both falling and rising edge. int0 37 1 in interrupt request pin 0: interrupt request pin with programmable level or rising-edge. am0,1 80, 78 2 in address mode selection: connect am0 pin to l and am1 pin to h for single chip mode. test0,1 76, 71 2 in test mode pins: should be tied to gnd. clk 77 1 out programmable clock output (with pull-up resistor) x1/x2 74, 72 2 in/out high-frequency oscillator connecting pins: to dr ive these pins with an external clock, apply clock signals of 3.3 v. xt1/xt2 70, 69 2 in/out low-frequency oscillator connecting pins: to dr ive these pins with an external clock, apply clock signals of 3.3 v. reset 79 1 in reset: initializes lsi (with pull-up resistor). vrefh 4 1 in ad reference voltage high vrefl 3 1 in ad reference voltage low advcc 2 1 - power supply pin for ad converter (+5v): connect the advcc pin to 5-v power supply. advss 1 1 - gnd pin for ad converter: connect the advss pin to gnd (0v). nmi int0 tmp92cd54i 2009-12-26 92cd54i-8 tentative table 2.2.4 input/output pins (4/4) pin name pin number number of pins in/out function dvcc5 15, 40, 50, 61, 75 5 - power supply pins (+5v): c onnect all the dvcc5 pins to 5-v power supply. dvcc3 36, 68, 86 3 - power supply pins (+3.3v): connect all the dvcc3 pins to regout pin. dvss 13, 38, 51, 63, 73, 88 6 - gnd: connect all dvss pins to gnd (0v). regout 49 1 out regulator output 3.3v: connect capacitor to stabilize the regulator output. regen 52 1 in regulator enable pin: should be set to h or open (with pull-up resistor). tmp92cd54i 2009-12-26 92cd54i-9 tentative 3. operation this section describes the basic functions and oper ations of the tmp92cd54i for each functional block. 3.1 cpu the tmp92cd54i incorporates a high-performan ce, high-speed 32-bit cpu, the tlcs-900/h1. 3.1.1 cpu overview the tlcs-900/h1 is a high-performance, high-speed cpu based on the tlcs-900/l1 and has a built-in data bus extended to 32 bits to enable faster processing. table 3.1.1 shows an overview of the cpu built into the tmp92cd54i.: table 3.1.1 cpu overview properties tlcs-900/h1 width of cpu address bus 24 bit width of cpu data bus 32 bit internal operating frequency 16 to 20mhz (f osc = 8 to 10mhz) minimum bus cycle (internal ram) 1 clock access (50ns @ f osc = 10mhz) internal ram 32 bit 1 clock access internal rom 32 bit interleave 2-1-1-1 clock access 8/16 bit 2 clock access port, intc, memc internal i/o 8/16 bit 5 to 6 clock access sei, sio, wdt, 8 bit timer, 16 bit timer, rtc, 10-bit adc, sbi, can external device 8 bit 2 clock access (can insert wait cycles) minimum instruction execution cycle 1 clock (50ns at f osc = 10mhz) conditional jump 2 clock (100ns at f osc = 10mhz) instruction queue buffer 12 byte instruction set compatible with tlcs-900, 900/h, 900/l, 900/l1 and 900/h2 (normal, min, max and ldx instructions are not supported) micro dma 8 channels tmp92cd54i 2009-12-26 92cd54i-10 tentative 3.1.2 reset to apply a reset to the tmp92cd54i, drive the reset input pin low for at least 4 s (when f osc = 10 mhz) when the internal oscillator and clock multiplier are operating stably with the supply voltage in the normal operating range. the clock multiplier is bypassed during the reset period so that the system clock frequency, f c , becomes 5 mhz (when f osc = 10 mhz). when a reset is accepted, the cpu operates as follows: ? sets the program counter (pc) as follows in accordance with the reset vector stored at address ffff00h to ffff02h: pc<0 to 7> data in location ffff00h pc<8 to 15> data in location ffff01h pc<16 to 23> data in location ffff02h ? sets the stack pointer (xsp) to 00000000h. ? sets bits tmp92cd54i 2009-12-26 92cd54i-11 tentative 3.1.3 selecting a startup mode set test0 and test1 to gnd, am0 to low and am1 to high to select single-chip mode. . table 3.1.2 operation mode setup mode setup input pin operation mode reset am1 am0 test1 test0 single-chip mode h l l l tmp92cd54i 2009-12-26 92cd54i-12 tentative 3.2 memory map figure 3.2.1 shows a memory map of the tmp92cd541i. 000000h 000400h 16mbyte area (r) ( ? r) (r + ) (r + r8/16) (r + d8/16) (nnn) direct area (n) 64kbyte area (nn) 512 kbyte internal rom internal i/o (1 kbyte) internal ram (32 kbyte) 008400h 010000h f80000h ( = internal area) ffff00h ffffffh vector table (256 byte) external memory 000100h emulator control area (64k byte) figure 3.2.1 memory map note 1: when an emulator is used, 64 kbytes of the 16-mbyte space are used to control the emulator and not available to the user. note 2: accessing the emulator control space causes the wr and rd signals to be output. this should be taken into account when using expanded memory. note 3: the last 16 bytes (addresses fffff0h to ffffffh) in the vector table are reserved as internal space and cannot be used. note 4: if memory devices having different bus widths are located at contiguous addresses, any access spanning those devices should not be executed with a single in struction. such an attempt may prevent data from being read or written normally. ( note1 ) (note2) tmp92cd54i 2009-12-26 92cd54i-13 tentative 3.3 clock function and standby functions 3.3.1 system clock block diagram figure 3.3.1 block diagram of system clock 10mhz 2/5 sei 16mhz system clock ?fc? clock doubler (pll) 4 (40mhz) 10mhz (10mhz) high frequency osc 20mhz 1/2 cpu memc intc romc port can sio timer wdt sbi a/d rtc x2 x1 for rtc 14-sta g e binar y counte r 32.768 khz (32.768 khz) ?fs? xt2 xt1 low frequency osc to generate the external memory interface timing 1/2 tmp92cd54i 2009-12-26 92cd54i-14 tentative 3.3.2 standby controller (1) halt mode executing the halt instruction (stop instruction) sets the operating mode to any of idle2, idle1, idle3 and stop depending on the setting of clkmod tmp92cd54i 2009-12-26 92cd54i-15 tentative the following shows whether individual blocks operate or stop in each mode: 1. idle2 mode: only the cpu is stopped. each built-in i/o block has a bit that controls whether it operates or stops in idle2 mode. the bits shown in table 3.3.1 are used to co ntrol the operation of built-in i/o blocks. table 3.3.1 the registers to control operation during idle2 mode internal i/o sfr registers timer0,timer1 trun01 tmp92cd54i 2009-12-26 92cd54i-16 tentative (2) releasing a halt mode a halt mode can be released with a reset or an interrupt request. available halt release sources depend on the state of the interrupt mask register tmp92cd54i 2009-12-26 92cd54i-17 tentative table 3.3.3 source of halt state cl earance and halt clearance operation status of received interrupt interrupt enabled (interrupt level) (interrupt mask) interrupt disabled (interrupt level) < (interrupt mask) halt mode idle2 idle1 idle3 stop idle2 idle1 idle3 stop nmi intwdt *1 *1 ? ? ? ? ? ? ? ? int0 *1 *2 *1 *2 { { { *1 *2 { *1 *2 int0 [mask] { { { *1 *2 { *1 *2 { { { *1 *2 { *1 *2 int1 to 7 intt0 to 7 inttr8 to b intto8, inttoa intrx0 to 1, tx0 to 1 intcr0, intct0, intcg0 intsem0, e0, r0, t0 intsbe0, s0, e1, s1, e2, s2 intad all the above-mentioned interrupts [mask] intrtc *1 { { { *1 interrupt source intrtc [mask] { { { *1 { { { *1 source of halt state clearance reset : upon release from a halt, the cpu starts handling the interrupt (reset causes the device to be initialized). { : upon release from a halt, the cpu starts processing from the instruction next to the halt instruction. : cannot be used to release a halt. ? : these combinations are not available because the in terrupt priority level (interrupt request level) for nonmaskable interrupts is fixed to 7 (top priority). *1: a halt is released after a warm-up time elapses. *2: any wuint interrupt (wuint0 to 7) causes an int0 interrupt to occur. note 1: to release a halt using a level-mode int0 interrupt in the interrupt-enabl ed state, hold it high until interrupt handling starts. if it is driven low before interrupt handling starts, the interrupt cannot be handled normally. note 2: when using an int5 to int7 external interrupt in idle2 mode, set trun8 tmp92cd54i 2009-12-26 92cd54i-18 tentative (3) operation in each mode 1. idle2 mode in idle2 mode, the system clock is supplied only to the built-in i/o blocks specified with the built-in i/o operation control bits and the cpu stops executing instructions. figure 3.3.3 shows an example timing for releasing a halt state using an interrup. n e x t n e x t + 4 fc a0 to 23 rd wr d0 to 31 data data halt instruction execution sequence clearing interrup t interrupt response se q uence figure 3.3.3 timing chart for idle2 mode halt state cleared by interrupt 2. idle1 mode in idle1 mode, only the internal oscillator operates with the system clock for the cpu stopped. in the halt state, interrupt request sampling is performed asynchronously to the system clock. the halt state is, however, released in sync with the system clock. figure 3.3.4 shows an example timing for releasing a halt state using an interrupt. n e x t n e x t + 4 fc a0 to 23 rd wr d0 to 31 data data halt instruction execution sequence clearing interrup t interrupt response se q uence figure 3.3.4 timing chart for idle1 mode halt state cleared by interrupt internal signals internal signals tmp92cd54i 2009-12-26 92cd54i-19 tentative 3. idle3 mode in idle3 mode, all internal circuits other than the low-speed oscillator and rtc, including the high-speed oscillator, are stopped. the pin states in idle3 mode depends on the setting of wdmod tmp92cd54i 2009-12-26 92cd54i-20 tentative 4. stop mode in stop mode, all internal circuits are stopped. the pin states in stop mode depends on the setting of wdmod tmp92cd54i 2009-12-26 92cd54i-21 tentative table 3.3.5 pin states in idle3 and stop mode pin names i/o tmp92cd54i 2009-12-26 92cd54i-22 tentative 3.4 interrupts interrupts for the tlcs-900/h1 are controlled using the cpu interrupt mask flip-flop (sr tmp92cd54i 2009-12-26 92cd54i-23 tentative figure 3.4.1 interrupt and micro dma processing sequence general-purpose interrupt processing yes push pc push sr sr tmp92cd54i 2009-12-26 92cd54i-24 tentative 3.4.1 general-purpose interrupt handling when the cpu accepts an interrupt, it performs the following operation. for software interrupts issued by the cpu and undefined instruction execution interrupts, the cpu only performs steps (2), (4), and (5) without executing steps (1) and (3). the following steps are similar to those for the tlcs-900/l, tlcs-900/h, tlc s-900/l1, and tlcs-900/h2. (1) the cpu reads an interrupt vector from the interrupt controller. if two or more interrupts having the same priority level occur simultaneously, the cpu issues an interrupt vector according to the de fault priorities (fixed: smaller vector values have higher priority) and clears the interrupt request. (2) the cpu pushes the program counter (pc) and status register (sr) into the stack area (pointed to by xsp). (3) set the cpu interrupt mask register sr tmp92cd54i 2009-12-26 92cd54i-25 tentative table 3.4.1 tmp92cd54i interrupt vectors and micro dma start vectors default priority type interrupt source and source of micro dma request vector value address refer to vector micro dma start vector 1 reset or [swi0] instruction 0000h ffff00h 2 [swi1] instruction 0004h ffff04h 3 illegal instruction or [swi2] instruction 0008h ffff08h 4 [swi3] instruction 000ch ffff0ch 5 [swi4] instruction 0010h ffff10h 6 [swi5] instruction 0014h ffff14h 7 [swi6] instruction 0018h ffff18h 8 [swi7] instruction 001ch ffff1ch 9 nmi: pin input 0020h ffff20h 10 non maskable intwd: watchdog timer 0024h ffff24h - micro dma - - - 11 int0: int0 pin input (note2) 0028h ffff28h 0ah 12 int1: int1 pin input 002ch ffff2ch 0bh 13 int2: int2 pin input 0030h ffff30h 0ch 14 int3: int3 pin input 0034h ffff34h 0dh 15 int4: int4 pin input 0038h ffff38h 0eh 16 int5: int5 pin input 003ch ffff3ch 0fh 17 int6: int6 pin input 0040h ffff40h 10h 18 int7: int7 pin input 0044h ffff44h 11h 19 intt0: 8-bit timer 0 0048h ffff48h 12h 20 intt1: 8-bit timer 1 004ch ffff4ch 13h 21 intt2: 8-bit timer 2 0050h ffff50h 14h 22 intt3: 8-bit timer 3 0054h ffff54h 15h 23 intt4: 8-bit timer 4 0058h ffff58h 16h 24 intt5: 8-bit timer 5 005ch ffff5ch 17h 25 intt6: 8-bit timer 6 0060h ffff60h 18h 26 intt7: 8-bit timer 7 0064h ffff64h 19h 27 inttr8: 16-bit timer 8 0068h ffff68h 1ah 28 inttr9: 16-bit timer 8 006ch ffff6ch 1bh 29 inttra: 16-bit timer a 0070h ffff70h 1ch 30 inttrb: 16-bit timer a 0074h ffff74h 1dh 31 intto8: 16-bit timer 8 (overflow) 0078h ffff78h 1eh 32 inttoa: 16-bit timer a (overflow) 007ch ffff7ch 1fh 33 intrx0: serial receive (channel 0) 0080h ffff80h 20h (note3) 34 inttx0: serial transmission (channel 0) 0084h ffff84h 21h 35 intrx1: serial receive (channel 1) 0088h ffff88h 22h (note3) 36 inttx1: serial transmission (channel 1) 008ch ffff8ch 23h 37 intcr: can receive 0090h ffff90h 24h (note3) 38 intct: can transmission 0094h ffff94h 25h (note3) 39 intcg: can global 0098h ffff98h 26h (note3) 40 intsem: sei mode fault error 009ch ffff9ch 27h (note3) 41 intsee: sei transfer end / slave error 00a0h ffffa0h 28h (note3) 42 intser: sei receive 00a4h ffffa4h 29h 43 intset: sei transmission 00a8h ffffa8h 2ah 44 intrtc: read time counter 00ach ffffach 2bh 45 (reserved) 00b0h ffffb0h - 46 intsbe2: sbi i2cbus transfer e nd (channel 2) 00b4h ffffb4h 2dh 47 intsbs2: sbi i2cbus stop conditi on (channel 2) 00b8h ffffb8h 2eh 48 intsbe0: sbi i2cbus transfer end (channel 0) 00bch ffffbch 2fh 49 intsbs0: sbi i2cbus stop condition (channel 0) 00c0h ffffc0h 30h 50 maskable intsbe1: sbi i2cbus transfer end (channel 1) 00c4h ffffc4h 31h tmp92cd54i 2009-12-26 92cd54i-26 tentative default priority type interrupt source and source of micro dma request vector value address refer to vector micro dma start vector 51 intsbs1: sbi i2cbus stop conditi on (channel 1) 00c8h ffffc8h 32h 52 intad: ad conversion end 00cch ffffcch 33h 53 inttc0: micro dma end (channel 0) 00d0h ffffd0h 34h 54 inttc1: micro dma end (channel 1) 00d4h ffffd4h 35h 55 inttc2: micro dma end (channel 2) 00d8h ffffd8h 36h 56 inttc3: micro dma end (channel 3) 00dch ffffdch 37h 57 inttc4: micro dma end (channel 4) 00e0h ffffe0h 38h 58 inttc5: micro dma end (channel 5) 00e4h ffffe4h 39h 59 inttc6: micro dma end (channel 6) 00e8h ffffe8h 3ah 60 inttc7: micro dma end (channel 7) 00ech ffffech 3bh ? to ? maskable (reserved) 00f0h to 00fch fffff0h to fffffch ? to ? note1: to start micro dma, select edge detection mode. note2: micro dma processing cannot be assigned. note3: if an interrupt occurs with an interrupt source specified for micro dma, it is given the highest priority among maskable interrupts (independently of the default priority assigned to each channel). note4: the above table lists only start addresses. each vector consists of four bytes. tmp92cd54i 2009-12-26 92cd54i-27 tentative 3.4.2 micro dma the tmp92cd54i supports the micro dma function . interrupt requests specified for the micro dma function are handled with the highest priority among maskable interrupts regardless of the set interrupt level. eight channels are provided for micro dma and support continuous transfer using a burst specification, described later. (1) micro dma operation when an interrupt request specified with the micro dma start vector register is issued, the micro dma function transfers data to the cp u with the highest priority among maskable interrupts regardless of the interrupt level assign ed to the interrupt source. if sr tmp92cd54i 2009-12-26 92cd54i-28 tentative the transferred data counter consists of 16 bits so that up to 65536 micro dma transfers can be performed for a single inte rrupt source (the maximum numbe r is allowed when the initial value of the counter is 0000h). micro dma supports 44 types of interrupt sources: 43 sources listed in table 3.4.1 with micro dma start vectors, plus soft start. figure 3.4.2 shows micro dma cycles in transfer address inc mode (similar in other modes, except counter mode) (with an 8-bit external bus, 0 waits, and even-numbered source and destination addresses). src one state clk a0 23 1 2 3 4 5 dst figure 3.4.2 timing for micro dma cycle 1st and 2nd states: instruction fetch cycle (prefetch the next instruction code) if the instruction queue buffer is full, this cycle becomes a dummy cycle. 3rd state: micro dma read cycle 4th state: micro dma write cycle 5th state: (same as 1st and 2nd states) (2) soft start function the tmp92cd54i supports a micro dma soft start function, which starts micro dma when a dmar register write cycle occurs rather than when an interrupt request is issued. specifically, a write of 1 to a bit in the dmar register can start a single micro dma transfer. upon the completion of transfer, the dmar register bit corresponding to the transferred channel is automatically cleared to 0. rewriting a 1 to the dmar register can perform a soft start again unless the micro dma transfer counter is 0. if a burst is specified with the dmar register, once micro dma is started, data is transferred continuously until the mi cro dma transfer counter becomes 0. symbol name address 7 6 5 4 3 2 1 0 dreq7 dreq6 dreq5 dreq4 dreq3 dreq2 dreq1 dreq0 r/w dmar dma request 109h (no rmw) 0 0 0 0 0 0 0 0 rmw prohibited: a read-modify-write operation cannot be performed. figure 3.4.3 micro dm a request register tmp92cd54i 2009-12-26 92cd54i-29 tentative (3) transfer control registers the following registers specify the transfer so urce and destination addresses. the ldc cr,r instruction is used to set data in these registers. channel 0 dmas0 dma source address register 0 dmad0 dma destination address register 0 dmac0 dma counter register 0 dmam0 dma mode register 0 channel 7 dmas7 dma source address register 7 dmad7 dma destination address register 7 dmac7 dma counter register 7 dmam7 dma mode register 7 8 bits 16 bits 32 bits figure 3.4.4 micro dm a transfer register tmp92cd54i 2009-12-26 92cd54i-30 tentative (4) details of transf er mode registers 0 0 0 mode dmam0 to 7 dmam[4:0] mode description execution time 0 0 0 z z destination inc mode (dmadn +) (dmasn) dmacn dmacn - 1 if dmacn = 0 then inttcn 5states 0 0 1 z z destination dec mode (dmadn -) (dmasn) dmacn dmacn - 1 if dmacn = 0 then inttcn 5states 0 1 0 z z source inc mode (dmadn) (dmasn +) dmacn dmacn - 1 if dmacn = 0 then inttcn 5states 0 1 1 z z source dec mode (dmadn) (dmasn -) dmacn dmacn ? 1 if dmacn = 0 then inttcn 5states 1 0 0 z z source and destination inc mode (dmadn +) (dmasn +) dmacn dmacn ? 1 if dmacn = 0 then inttcn 6states 1 0 1 z z source and destination dec mode (dmadn -) (dmasn -) dmacn dmacn ? 1 if dmacn = 0 then inttcn 6states 1 1 0 z z destination and fixed mode (dmadn) (dmasn) dmacn dmacn ? 1 if dmacn = 0 then inttcn 5states counter mode 1 1 1 z z dmasn dmasn + 1 dmacn dmacn ? 1 if dmacn = 0 then inttcn 5states zz: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (reserved) note1: the execution times shown above are best-c ase values (assuming that memory access is completed in a single clock cycle). 1 state = 50 ns (when fc = 20 mhz) note2: n indicates the micro dma channel number (0 to 7). dmadn+/dmasn+: post-increment (register value is incremented after transfer) dmadn-/dmasn-: post-decrement (register value is decremented after transfer) figure 3.4.5 details of transfer mode registers tmp92cd54i 2009-12-26 92cd54i-31 tentative 3.4.3 control by the interrupt controller figure 3.4.16 shows a block diagram of the interrupt circuit. the left half of the figure represents the interrupt controller while th e right half represents the cpu interrupt request signal circuit and halt release circuit. the interrupt controller has an interrupt reques t flag, interrupt priority setup register and micro dma start vector setup register for each interrupt channel (51 channels in total). the interrupt request flag is used to latch an interrupt request from a peripheral device. this flag is cleared under the following conditions: ? upon a reset ? when the cpu accepts the interrupt and reads the vector for that interrupt. ? when the instruction that clears the interrupt is executed (the micro dma start vector for the interrupt source to be cleared is written to the intclr register). ? the cpu accepts a micro dma request for that interrupt. ? the micro dma burst transfer for that interrupt is completed. interrupt priorities can be set by writing th em to the interrupt priority setup registers (inte0ad, inte12, and so on) that are provided for each interrupt source. one of six interrupt levels, 1 to 6, can be set. writing a priority le vel of 0 (or 7) causes th e corresponding interrupt request to be disabled. nonmaskable interrupts (n mi pin) have a fixed priority level of 7. if more than one interrupt request having the same priority level occurs simultaneously, the cpu accepts an interrupt according to the default priorities (lower priority value = smaller vector). reading bits 3 and 7 in the interrupt priority setup register returns the state of the interrupt request flag, which indicates whether an interrupt request has been issued for each channel. among the interrupts that have occurred simult aneously, the interrupt controller sends the highest interrupt priority level and its vector address to the cpu. the cpu compares the sent interrupt level with the interrupt mask register va lue tmp92cd54i 2009-12-26 92cd54i-32 tentative interrupt request si g nal to cpu if 1 Q iff2:0 Q 6 then 1. micro dma start vector setting register inttc0 inttc1 inttc2 inttc3 inttc4 inttc5 inttc6 inttc7 v = d0h v = d4h v = d8h v = dch v = e0h v = e4h v = e8h v = ech soft start micro dm a counte r zero interrupt 6 inttc0 during idle1 51 3 3 3 1 6 1 7 3 3 8 6 6 8 input or int0 micro dma channel priority encoder priority encoder dma0v dma1v : dma7v reset interrupt request f/f reset decoder reset priority setting register v = 20h v = 24h interrupt controller cpu s q r v = 28h v = 2ch v = 30h v = 34h v = 38h v = 3ch v = 40h v = 44h v = 48h v = 4ch d q clr y1 y2 y3 y4 y5 y6 a b c dn dn + 1 dn + 2 interrupt request f/f interrupt vector read micro dma acknowledge interrupt request f/f dn + 3 a b c interrupt vector read d2 d3 d4 d5 d6 d7 match detect s q r 0 1 2 3 4 5 6 7 a b c d0 d1 interrupt vecto r v read interrupt mask f/f micro dma request halt release nmi if intrq2:0 R iff2:0 then 1. intrq2 to 0 iff2:0 interrupt level detect reset ei 1 to 7 di interrupt request signal during stop micro dma channel specification reset nmi intwd int0 int1 int2 int3 int4 int5 int6 int7 intt0 intt1 interrupt vector generator highest priority interrupt level select 1 2 3 4 5 6 7 d5 d4 d3 d2 d1 d0 d q clr 6 figure 3.4.6 block diagram of interrupt controller tmp92cd54i 2009-12-26 92cd54i-33 tentative (1) interrupt priority setup registers symbol name address 7 6 5 4 3 2 1 0 intad int0 (note) iadc iadm2 iadm1 iadm0 i0c i0m2 i0m1 i0m0 r r/w r r/w inte0ad int0 & intad enable f0h 0 0 0 0 0 0 0 0 int2 int1 i2c i2m2 i2m1 i2m0 i1c i1m2 i1m1 i1m0 r r/w r r/w inte12 int1 & int2 enable d0h 0 0 0 0 0 0 0 0 int4 int3 i4c i4m2 i4m1 i4m0 i3c i3m2 i3m1 i3m0 r r/w r r/w inte34 int3 & int4 enable d1h 0 0 0 0 0 0 0 0 int6 int5 i6c i6m2 i6m1 i6m0 i5c i5m2 i5m1 i5m0 r r/w r r/w inte56 int5 & int6 enable d2h 0 0 0 0 0 0 0 0 int7 - - - - i7c i7m2 i7m1 i7m0 r r/w inte7 int7 enable d7h - - - - 0 0 0 0 intt1(timer1) intt0(timer0) it1c it1m2 it1m1 it1m0 it0c it0m2 it0m1 it0m0 r r/w r r/w intet01 intt0 & intt1 enable d4h 0 0 0 0 0 0 0 0 intt3(timer3) intt2(timer2) it3c it3m2 it3m1 it3m0 it2c it2m2 it2m1 it2m0 r r/w r r/w intet23 intt2 & intt3 enable d5h 0 0 0 0 0 0 0 0 intt5(timer5) intt4(timer4) it5c it5m2 it5m1 it5m0 it4c it4m2 it4m1 it4m0 r r/w r r/w intet45 intt4 & intt5 enable d6h 0 0 0 0 0 0 0 0 intt7(timer7) intt6(timer6) it7c it7m2 it7m1 it7m0 it6c it6m2 it6m1 it6m0 r r/w r r/w intet67 intt6 & intt7 enable d7h 0 0 0 0 0 0 0 0 inttr9(timer8) inttr8(timer8) it9c it9m2 it9m1 it9m0 it8c it8m2 it8m1 it8m0 r r/w r r/w intet89 inttr8 & inttr9 enable d8h 0 0 0 0 0 0 0 0 inttrb(timera) inttra(timera) itbc itbm2 itbm1 itbm0 itac itam2 itam1 itam0 r r/w r r/w intetab inttra & inttrb enable d9h 0 0 0 0 0 0 0 0 inttoa intto8 itoac itoam2 itoam1 itoam0 ito8c ito8m2 ito8m1 ito8m0 r r/w r r/w inteto8a intto8 & inttoa (overflow) enable dah 0 0 0 0 0 0 0 0 note 1: if any bit of wupmask tmp92cd54i 2009-12-26 92cd54i-34 tentative symbol name address 7 6 5 4 3 2 1 0 inttx0 intrx0 itx0c itx0m2 itx0m1 itx0m0 irx0c irx0m2 irx0m1 irx0m0 r r/w r r/w intes0 intrx0 & inttx0 enable dbh 0 0 0 0 0 0 0 0 inttx1 intrx1 itx1c itx1m2 itx1m1 itx1m0 irx1c irx1m2 irx1m1 irx1m0 r r/w r r/w intes1 intrx1 & inttx1 enable dch 0 0 0 0 0 0 0 0 intct intcr ictc ictm2 ictm1 ictm0 icrc icrm2 icrm1 icrm0 r r/w r r/w intecrt intcr & intct enable ddh 0 0 0 0 0 0 0 0 intcg - - - - icgc icgm2 icgm1 icgm0 r r/w intecg intcg enable deh - - - - 0 0 0 0* intsee0 intsem0 isee0c isee0m2 isee0m1 isee0m0 isem0c isem0m2 isem0m1 isem0m0 r r/w r r/w intesee0 intsem0 & intsee0 enable dfh 0 0 0 0 0 0 0 0 intset0 intser0 iset0c iset0m2 iset0m1 iset0m0 iser0c iser0m2 iser0m1 iser0m0 r r/w r r/w intesed0 intser0 & intset0 enable e0h 0 0 0 0 0 0 0 0 intrtc - - - - irtcc irtcm2 irtcm1 irtcm0 r r/w intertc intrtc enable e1h - - - - 0 0 0 0 intsbs2 intsbe2 isbs2c isbs2m2 isbs2m1 isbs2m0 isbe2c isbe2m2 isbe2m1 isbe2m0 r r/w r r/w intesb2 intsbe2 & intsbs2 enable e2h 0 0 0 0 0 0 0 0 intsbs0 intsbe0 isbs0c isbs0m2 isbs0m1 isbs0m0 isbe0c isbe0m2 isbe0m1 isbe0m0 r r/w r r/w intesb0 intsbe0 & intsbs0 enable e3h 0 0 0 0 0 0 0 0 intsbs1 intsbe1 isbs1c isbs1m2 isbs1m1 isbs1m0 isbe1c isbe1m2 isbe1m1 isbe1m0 r r/w r r/w intesb1 intsbe1 & intsbs1 enable e4h 0 0 0 0 0 0 0 0 inttc1(dma1) inttc0(dma0) itc1c itc1m2 itc1m1 itc1m0 itc0c itc0m2 itc0m1 itc0m0 r r/w r r/w intetc01 inttc0 & inttc1 enable f1h 0 0 0 0 0 0 0 0 inttc3(dma3) inttc2(dma2) itc3c itc3m2 itc3m1 itc3m0 itc2c itc2m2 itc2m1 itc2m0 r r/w r r/w intetc23 inttc2 & inttc3 enable f2h 0 0 0 0 0 0 0 0 inttc5(dma5) inttc4(dma4) itc5c itc5m2 itc5m1 itc5m0 itc4c itc4m2 itc4m1 itc4m0 r r/w r r/w intetc45 inttc4 & inttc5 enable f3h 0 0 0 0 0 0 0 0 inttc7(dma7) inttc6(dma6) itc7c itc7m2 itc7m1 itc7m0 itc6c itc6m2 itc6m1 itc6m0 r r/w r r/w intetc67 inttc6 & inttc7 enable f4h 0 0 0 0 0 0 0 0 figure 3.4.8 interrupt prio rity setup registers (2/3) tmp92cd54i 2009-12-26 92cd54i-35 tentative symbol name address 7 6 5 4 3 2 1 0 nmi intwd inmic - - - iwdc - - - r r intnmwdt nmi & intwd enable f7h 0 - - - 0 - - - lxxm2 lxxm1 lxxm0 function ( write ) 0 0 0 disables interrupt requests 0 0 1 sets interrupt priority level to 1 0 1 0 sets interrupt priority level to 2 0 1 1 sets interrupt priority level to 3 1 0 0 sets interrupt priority level to 4 1 0 1 sets interrupt priority level to 5 1 1 0 sets interrupt priority level to 6 1 1 1 disables interrupt requests note: to modify an interrupt priority setup register, first execute the di instruction to disable the acceptance of interrupts. figure 3.4.9 interrupt prio rity setup registers (3/3) (2) controlling external interrupts symbol name address 7 6 5 4 3 2 1 0 - - - - - - i0le nmiree r/w - - - - - - 0 0 iimc interrupt input mode control f6h (no rmw) i n t 0 m o d e 0:edge mode 1:level mode nmi mode 0:falling edge 1:falling & rising edges int0 level enable 0 rising edge detect int 1 ?h? level int nmi rising edge enable 0 int request generation at falling edge 1 int request generation at rising and falling edge note 1: to switch the int0 pin mode from level to edge (iimc tmp92cd54i 2009-12-26 92cd54i-36 tentative table 3.4.2 settings of external interrupt pin function interrupt pin name mode setting method fallin g ed g e iimc tmp92cd54i 2009-12-26 92cd54i-37 tentative (3) interrupt request flag register the interrupt request flag can be cleared by wr iting a micro dma start vector, listed in table 3.4.1, to the intclr register. to clear the int0 interrupt flag, for example, perform the following register operation after the di instruction: intclr 0ah ; clear int0 interrupt request flag symbol name address 7 6 5 4 3 2 1 0 - - - - - - - - w 0 0 0 0 0 0 0 0 intclr interrupt clear control f8h (no rmw) interrupt vector figure 3.4.11 interrupt request flag register (4) micro dma start vector registers the micro dma start vector registers are used to select the interrupt sources to which micro dma processing is assi gned. interrupt sources having micro dma start vectors that match the vector values in the registers are assigned as micro dma start sources. when the micro dma transfer counter becomes 0, th e interrupt controller is notified of a micro dma transfer completion interrupt for that channel and the corresponding micro dma start vector register is cleared, causing the micro dma start source for the channel to be cleared. to continue micro dma processing, therefore, it is necessary to set the micro dma start vector register again while the micro dma transfer completion interrupt is handled. if the same vector is set in micro dma start vect or registers for more than one channel, smaller channels take precedence. if the same vector is set in micro dma start vector register for two channels, therefore, micro dma for the channel having the smaller number is performed until the micro dma transfer completion interrupt is issued, after which micro dma is started for the larger-number channel unless the micro dma start vector for th e smaller-number channel is set again. tmp92cd54i 2009-12-26 92cd54i-38 tentative symbol name address 7 6 5 4 3 2 1 0 dma0 start vector - - dma0v5 dma0v4 dma0v3 dma0v2 dma0v1 dma0v0 r/w dma0v dma0 start vector 100h (no rmw) - - 0 0 0 0 0 0 dma1 start vector - - dma1v5 dma1v4 dma1v3 dma1v2 dma1v1 dma1v0 r/w dma1v dma1 start vector 101h (no rmw) - - 0 0 0 0 0 0 dma2 start vector - - dma2v5 dma2v4 dma2v3 dma2v2 dma2v1 dma2v0 r/w dma2v dma2 start vector 102h (no rmw) - - 0 0 0 0 0 0 dma3 start vector - - dma3v5 dma3v4 dma3v3 dma3v2 dma3v1 dma3v0 r/w dma3v dma3 start vector 103h (no rmw) - - 0 0 0 0 0 0 dma4 start vector - - dma4v5 dma4v4 dma4v3 dma4v2 dma4v1 dma4v0 r/w dma4v dma4 start vector 104h (no rmw) - - 0 0 0 0 0 0 dma5 start vector - - dma5v5 dma5v4 dma5v3 dma5v2 dma5v1 dma5v0 r/w dma5v dma5 start vector 105h (no rmw) - - 0 0 0 0 0 0 dma6 start vector - - dma6v5 dma6v4 dma6v3 dma6v2 dma6v1 dma6v0 r/w dma6v dma6 start vector 106h (no rmw) - - 0 0 0 0 0 0 dma7 start vector - - dma7v5 dma7v4 dma7v3 dma7v2 dma7v1 dma7v0 r/w dma7v dma7 start vector 107h (no rmw) - - 0 0 0 0 0 0 figure 3.4.12 micro dma start vector registers (5) micro dma burst specification a burst specification allows data to be transfer red continuously with a single micro dma start until the transfer count register becomes zero. a burst can be specified by writing a 1 to the bit corresponding to the micro dma channel in the dmab register. symbol name address 7 6 5 4 3 2 1 0 dbst7 dbst6 dbst5 dbst4 d bst3 dbst2 dbst1 dbst0 r/w dmab dma burst 108h (no rmw) 0 0 0 0 0 0 0 0 figure 3.4.13 micro dma burst specification tmp92cd54i 2009-12-26 92cd54i-39 tentative (6) precautions this cpu consists of an instruction execution unit and a bus interface unit. if an instruction that clears the interrupt request flag for the interrupt controller is executed immediately before a corresponding interrupt occurs, the cpu may ex ecute the instruction clearing the interrupt request flag(note) before it reads the interrupt ve ctor after accepting the interrupt. in such a case, the cpu reads the source lost vector "0004h" (shared with swi1) and then reads the interrupt vector at address ffff04h. to avoid the above situation, any instruction that clears an interrupt request flag should be placed after the di instruction. to change th e interrupt request level to 0, first clear the corresponding interrupt request using the intc lr instruction before setting the interrupt request level to 0. in addition, note that the following two interru pts are different from other interrupt circuits: in level mode int0 is not an edge-triggered interrupt. hence, in level mode the interrupt request flip -flop for int0 does not function. the peripheral interrupt request passes through the s input of the flip-flop and becomes the q output. if the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. int0 level mode if the cpu enters the interr upt response sequence as a result of int0 going from 0 to 1, int0 must then be held at 1 until the interrupt response sequence has been completed. if int0 is set to level mode so as to release a halt state, int0 must be held at 1 from the time int0 changes from 0 to 1 until the halt state is released. (hence, it is necessary to ensure that input noise is not interpreted as a 0, causing int0 to revert to 0 before the halt state has been released.) when the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. interrupt request flags must be cl eared using the fo llowing sequence. also ei instruction should be execuse after waiting 3-cycle. di ld (iimc), 00h ; switches from level to edge. ld (intclr), 0ah ; clears interrupt request flag. nop ; wait 3-cycle nop nop ei intrx the interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. it cannot be cleared by an instruction. note: the following instructions and pin state chang e are also equivalent to an instruction that clears an interrupt request flag: int0: instruction that switches to level mode af ter an interrupt request is issued in edge mode change in pin input state (high to low) after an interrupt request is issued in level mode intrx: instruction that reads the receive buffer tmp92cd54i 2009-12-26 92cd54i-40 tentative 3.4.4 interrupt mask registers the tmp92cd54i contains interrupt mask regi sters. unlike the interrupt priority setup registers, the interrupt mask registers only enable or disable interrupt handling. if an interrupt source is disabled in the interrupt mask register, interrupts for that source will not occur even if it is enabled in the inte rrupt priority setup register. interrupt mask registers can disable mo re than one interrupt source simultaneously. upon a reset, all bits in the interrupt mask registers are initialized to 1 (enable interrupts). to disable interrupts using the inte rrupt mask registers, it is necessary to write a 0 to the bit corresponding to the interrupt source. figure 3.4.14 block diagram of interrupt mask control 8-bit timer 16-bit timer rtc can sei sbi adc external interrupt int0 int1 int2 int3 int4 int5 int6 int7 sio intmk0 intmk1 intmk2 intmk3 intmk4 intmk5 8 1 6 3 4 4 1 6 8 1 6 3 4 4 1 6 8 6 1 4 3 4 6 1 8 6 1 4 3 4 6 1 41 interrupt controller tmp92cd54i 2009-12-26 92cd54i-41 tentative symbol name address 7 6 5 4 3 2 1 0 mki7 mki6 mki5 mki4 mki3 mki2 mki1 mki0 r/w 1 1 1 1 1 1 1 1 intmk0 interrupt mask control 0 e5h int7 0: mask 1: enable int6 0: mask 1: enable int5 0: mask 1: enable int4 0: mask 1: enable int3 0: mask 1: enable int2 0: mask 1: enable int1 0: mask 1: enable int0 0: mask 1: enable mkit7 mkit6 mkit5 mkit4 mkit3 mkit2 mkit1 mkit0 r/w 1 1 1 1 1 1 1 1 intmk1 interrupt mask control 1 e6h intt7 0: mask 1: enable intt6 0: mask 1: enable intt5 0: mask 1: enable intt4 0: mask 1: enable intt3 0: mask 1: enable intt2 0: mask 1: enable intt1 0: mask 1: enable intt0 0: mask 1: enable ? mkirtc mkitoa mkito8 mkitrb mkitra mkitr9 mkitr8 r/w ? 1 1 1 1 1 1 1 intmk2 interrupt mask control 2 e7h intrtc 0: mask 1: enable inttoa 0: mask 1: enable intto8 0: mask 1: enable inttrb 0: mask 1: enable inttra 0: mask 1: enable inttr9 0: mask 1: enable inttr8 0: mask 1: enable ? mkicg mkict mkicr mkitx1 mkirx1 mkitx0 mkirx0 r/w ? 1 1 1 1 1 1 1 intmk3 interrupt mask control 3 e8h intcg 0: mask 1: enable intct 0: mask 1: enable intcr 0: mask 1: enable inttx1 0: mask 1: enable intrx1 0: mask 1: enable inttx0 0: mask 1: enable intrx0 0: mask 1: enable ? ? ? ? mkiset0 mkiser0 mkisee0 mkisem0 r / w ? ? ? ? 1 1 1 1 intmk4 interrupt mask control 4 e9h i n t s e t 0: mask 1: enable intser 0: mask 1: enable intsee 0: mask 1: enable intsem 0: mask 1: enable ? mkisbs2 mkisbe2 mkiad mkisbs1 mkisbe1 mkisbs0 mkisbe0 r/w ? 1 1 1 1 1 1 1 intmk5 interrupt mask control 5 eah intsbs2 0: mask 1: enable intsbe2 0: mask 1: enable intad 0: mask 1: enable intsbs1 0: mask 1: enable intsbe1 0: mask 1: enable intsbs0 0: mask 1: enable intsbe0 0: mask 1: enable maskable bit for intad request 0 intad is disabled 1 intad is enabled note: ports d0, d1, and d4 are assigned two interrupt sour ces each (pd0: int5/wuint0, pd1: int6/wuint1, pd4: int7/wuint4). if both interrupt requests are issued when interrupts are enabled, both are handled. to use only either of the two interrupt sources, di sable (mask) the other interrupt source using the interrupt mask register or wakeup mask register. figure 3.4.15 interrupt mask registers tmp92cd54i 2009-12-26 92cd54i-42 tentative example register settings: to change the int0 interrupt priority level from 3 to 7, set as follows: di ; disable interrupt ld (intmk0), 00h ; disable int0 ld (inte0ad), 03h ; set int0 interrupt level to 3 ld (intclr), 0ah ; clear int0 interrupt request flag nop ; wait for 3 cycles nop nop ld (intmk0), 01h ; enable int0 ei ; enable interrupt : : ; programmed operation di ; disable interrupt ld (intmk0), 00h ; disable int0 ld (inte0ad), 07h ; set int0 interrupt level to 7 ld (intclr), 0ah ; clear int0 interrupt request flag nop ; wait for 3 cycles nop nop ld (intmk0), 01h ; enable int0 ei ; enable interrupt tmp92cd54i 2009-12-26 92cd54i-43 tentative 3.4.5 wakeup interrupt controller the tmp92cd54i has eight wakeup pins (wuint0-7). input signals to those pins can be used to recover from the halt state. these pins are shared with port d (pd0-7). the input signal attribute can be set to rising edge, falling edge or rising/falling edges, separately for each pin. the signals can also be masked on a pin-by-pin basis. figure 3.4.16 block diagram of on/off logic the wakeup interrupt controller internally sends all interrupt signals on wuint0-7 to int0. any wuintn request that has been issued causes an int0 interrupt to be issued. like int0 interrupt request from external pins, int0 interrupt requests from the wuintn pin are also enabled or disabled using the interrupt priority setup and interrupt mask registers. a write of 1 to any bit in the wupmask register causes int0 to be placed in wakeup interrupt mode. in this mode, the wuintn signal for which a 1 is written in the wupmask register becomes valid and the input signal from the external int0 pin is invalidated. to use the external int0 pin, set the wupmask register to 00h. the edge selection for the wuintn signal can be set to rising edge, falling edge or rising/falling edges using the wupmod and wupedge registers. reading the wupflag register can determin e whether a wuintn interrupt request has been issued. input signals detection circuit wupedge tmp92cd54i 2009-12-26 92cd54i-44 tentative wakeup flag status register 7 6 5 4 3 2 1 0 symbol wflg7 wflg6 wflg5 wf lg4 wflg3 wflg2 wflg1 wflg0 read/write r/w after reset 0 0 0 0 0 0 0 0 function wuint7 0:no request 1: request wuint6 0:no request 1: request wuint5 0:no request 1: request wuint4 0:no request 1: request wuint3 0:no request 1: request wuint2 0:no request 1: request wuint1 0:no request 1: request wuint0 0:no request 1: request wakeup mode control register 7 6 5 4 3 2 1 0 symbol wmd7 wmd6 wmd 5 wmd4 wmd3 wmd2 wmd1 wmd0 read/write r/w after reset 0 0 0 0 0 0 0 0 function wuint7 0:falling & rising edge 1:falling or rising edge wuint6 0:falling & rising edge 1:falling or rising edge wuint5 0:falling & rising edge 1:falling or rising edge wuint4 0:falling & rising edge 1:falling or rising edge wuint3 0:falling & rising edge 1:falling or rising edge wuint2 0:falling & rising edge 1:falling or rising edge wuint1 0:falling & rising edge 1:falling or rising edge wuint0 0:falling & rising edge 1:falling or rising edge wakeup edge select register 7 6 5 4 3 2 1 0 symbol wed7 wed6 wed 5 wed4 wed3 wed2 wed1 wed0 read/write r/w after reset 0 0 0 0 0 0 0 0 function wuint7 0:falling edge 1:rising edge wuint6 0:falling edge 1:rising edge wuint5 0:falling edge 1:rising edge wuint4 0:falling edge 1:rising edge wuint3 0:falling edge 1:rising edge wuint2 0:falling edge 1:rising edge wuint1 0:falling edge 1:rising edge wuint0 0:falling edge 1:rising edge note: the wupedge tmp92cd54i 2009-12-26 92cd54i-45 tentative example register settings: the following example sets wuint0 to rising edge and interrupt level 3: di ; disable interrupt handling ld (intmk0), 00h ; disable int0 ld (pdfc), 00h ; set pd0 to port ld (pdcr), 00h ; set pd0 to input mode ld (wupmod), 01h ; set wuint0 to "falling or rising edge" ld (wupedge), 01h ; set wuint0 to "rising edge" ld (wupflag), 00h ; clear wuint0 flag ld (inte0ad), 03h ; set int0 interrupt level (as wuint0) to 3 ld (intclr), 0ah ; clear int0 interrupt request flag nop ; wait for 3 cycles nop nop ld (intmk0), 01h ; enable wuint0 ei ; enable interrupt handling tmp92cd54i 2009-12-26 92cd54i-46 tentative 3.5 port functions the tmp92cd54i has input/output ports listed in table 3.5.1. these port pins are shared pins; they are not only used for general-purpose input/output port functions but also used as internal cpu or i/o function pins. table 3.5.1 port functions port name pin name number of pins i/o i/o setting pin name for built-in function port 0 p00 to p07 8 i/o bit d0 to d7 port 4 p40 to p47 8 i/o bit a0 to a7 p70 1 i/o bit rd p71 1 i/o bit wr p72 1 i/o bit si2/scl2 p73 1 i/o bit cs p74 1 i/o bit port 7 p75 1 i/o bit wait pc0 1 i/o bit ti0 / int1 pc1 1 i/o bit to1 pc2 1 i/o bit to3 / int2 pc3 1 i/o bit ti4 / int3 pc4 1 i/o bit to5 port c pc5 1 i/o bit to7 / int4 pd0 1 i/o bit ti8 / int5 / a16 / wuint0 pd1 1 i/o bit ti9 / int6 / a17 / wuint1 pd2 1 i/o bit to8 / a18 / wuint2 pd3 1 i/o bit to9 / a19 / wuint3 pd4 1 i/o bit tia / int7 / a20 / wuint4 pd5 1 i/o bit tib / a21 / wuint5 pd6 1 i/o bit toa / a22 / wuint6 port d pd7 1 i/o bit tob / a23 / wuint7 pf0 1 i/o bit txd0 pf1 1 i/o bit rxd0 pf2 1 i/o bit sclk0 / cts0 pf3 1 i/o bit txd1 pf4 1 i/o bit rxd1 pf5 1 i/o bit sclk1 / cts1 pf6 1 i/o bit tx port f pf7 1 i/o bit rx port g pg0 to pg7 8 input (fixed) an0 to an7 port l pl0 to pl3 4 input (fixed) an8 to an11 pm0 1 i/o bit ss / a8 pm1 1 i/o bit mosi / a9 pm2 1 i/o bit miso / a10 pm3 1 i/o bit seclk / a11 port m pm4 1 i/o bit sck2 pn0 1 i/o bit sck0 pn1 1 i/o bit so0 / sda0 pn2 1 i/o bit si0 / scl0 pn3 1 i/o bit sck1 / a12 pn4 1 i/o bit so1 / sda1 / a13 pn5 1 i/o bit si1 / scl1 / a14 port n pn6 1 i/o bit so2 / sda2 / a15 tmp92cd54i 2009-12-26 92cd54i-47 tentative 3.5.1 port 0 (p00-p07/d0-d7) port 0 is an 8-bit general-purpose input/ output port for which each bit can be individually specified as input or output. the control register, p0cr, and function register, p0fc, are used to specify input or output. in addition to the general-purpose input/output port function, the pins can also function as a data bus (d0-d7). figure 3.5.1 port0 table 3.5.2 port0 registers symbol name address 7 6 5 4 3 2 1 0 p07 p06 p05 p04 p03 p02 p01 p00 r/w 0 0 0 0 0 0 0 0 p0 port0 00h input/output p07c p06c p05c p04c p03c p02c p01c p00c w 0 0 0 0 0 0 0 0 p0cr port0 control register 02h (no rmw) 0:input 1:output ? ? ? ? ? ? ? p0f w ? ? ? ? ? ? ? 0 p0fc port0 function register 03h (no rmw) 0:port 1:data bus(d7 to d0) p0fc tmp92cd54i 2009-12-26 92cd54i-48 tentative 3.5.2 port 4 (p40-p47) port 4 is an 8-bit general-purpose input/ output port for which each bit can be individually specified as input or output. the control register, p4cr, and function register, p4fc, are used to specify input or output. in addition to the general-purpose input/output port function, the pins can also function as an address bus (a0-a7). figure 3.5.2 port4 table 3.5.3 port4 registers symbol name address 7 6 5 4 3 2 1 0 p47 p46 p45 p44 p43 p42 p41 p40 r/w 0 0 0 0 0 0 0 0 p4 port4 10h input/output p47c p46c p45c p44c p43c p42c p41c p40c w 0 0 0 0 0 0 0 0 p4cr port4 control register 12h (no rmw) 0:input 1:output p47f p46f p45f p44f p43f p42f p41f p40f w 0 0 0 0 0 0 0 0 p4fc port4 function register 13h (no rmw) 0:port 1:address bus(a0 to a7) p4fc tmp92cd54i 2009-12-26 92cd54i-49 tentative 3.5.3 port 7 (p70-p75) port 7 is an 6-bit general-purpose input/ output port for which each bit can be individually specified as input or output. the control register, p7cr, and function register, p7fc, are used to specify input or output. in addition to the general-purpose input/ou tput port function, pins 70, 71 and 73 can also function as read, write strobe and chip select signals respecti vely, pin 72 as an i/o pin for the clock synchronous 8-bit sio or the serial bus interface that operates as an i 2 c bus, and pin 75 as a wait input. the sbi data input (sio), si2, and sbi clock input/output (i 2 c), scl2, are always input-enabled. a reset initializes port pins 70, 71, 73 and 74 to output port mode and pins 72 and 75 to input port mode. figure 3.5.3 port7 (p70 to p72) p72 (si2/scl2) p7cr register p7fc register p7 register s 0 1 selector s 1 0 selecto r s 0 1 selector when pnode register is ?1?, p72 signal is open drain output. port read data (reserved) si/scl input scl output p7 register s 0 1 selector s 1 0 selector port read data p71 ( wr ) write strobe p7cr register p7fc register p7 register s 0 1 selector s 1 0 selector port read data p70 ( rd ) read strobe p7cr register p7fc register tmp92cd54i 2009-12-26 92cd54i-50 tentative figure 3.5.4 port7 (p73 to p75) p7 register s 0 1 selecto r s 1 0 selecto r p o r t r ead data p73 ( cs ) chip selection p7cr register p7fc register p7 register s 1 0 selector wait re q uest p75 ( wait ) p7cr register p7fc register port read data p7 register s 0 1 selecto r s 1 0 selecto r port read data p74 ( reserved ) p7cr register p7fc register tmp92cd54i 2009-12-26 92cd54i-51 tentative table 3.5.4 port7 registers symbol name address 7 6 5 4 3 2 1 0 ? ? p75 p74 p73 p72 p71 p70 r/w ? ? 0 1 1 1 1 1 p7 port7 1ch input/output ? ? p75c p74c p73c p72c p71c p70c w ? ? 0 1 1 0 1 1 p7cr port7 control register 1eh (no rmw) 0:input 1:output ? ? p75f p74f p73f p72f p71f p70f w ? ? 0 0 0 0 0 0 p7fc port7 function register 1fh (no rmw) 0:port 1: wait 0:port 0:port 1: cs 0:port 1:si2 scl2 note1 0:port 1: wr 0:port 1: rd p7cr p7fc ? ? p75 p74 p73 p72 p71 p70 0 0 input port input port, si2 input port 1 0 output port 1 1 wait don?t use this setting. cs don?t use this setting. wr rd 0 1 wait don?t use this setting. cs si2, scl2 wr rd note: the scl2 (p72) pin (clock input/output pin for i 2 c mode) can be set to open-drain by setting pnode tmp92cd54i 2009-12-26 92cd54i-52 tentative 3.5.4 port c (pc0-pc5) port c is an 6-bit general-purpose input/ output port for which each bit can be individually specified as input or output. the control register, pccr, and function register, pcfc, are used to specify input or output. in addition to the general-purpose input/output port function, the pins can also function as 8-bit timer input/output or interrupt input. timer inputs ti0 and ti4 are always input-enabled except when in idle3 or stop mode. a reset initializes port c to input port mode. figure 3.5.5 portc (pc0 to pc5) pc4 (to5) pc5 (to7/int4) pc register pccr register pcfc register s 0 1 timer output port read data s 1 0 interrupt request 1 0 s 1 0 s 1 0 pc1 (to1) pc2 (to3/int2) pc register pccr register pcfc register (reserved) port read data timer output s interrupt request pc register port read data timer input pc0 (ti0/int1) pc3 (ti4/int3) (reserved) s 1 0 pccr re g ister pcfc register s 1 0 interrupt request tmp92cd54i 2009-12-26 92cd54i-53 tentative table 3.5.5 portc registers symbol name address 7 6 5 4 3 2 1 0 ? ? pc5 pc4 pc3 pc2 pc1 pc0 r/w ? ? 0 0 0 0 0 0 pc portc 30h input/output ? ? pc5c pc4c pc3c pc2c pc1c pc0c w ? ? 0 0 0 0 0 0 pccr portc control register 32h (no rmw) 0:input 1:output ? ? pc5f pc4f pc3f pc2f pc1f pc0f w ? ? 0 0 0 0 0 0 pcfc portc function register 33h (no rmw) 0:port int4 1:to7 0:port 1:to5 0:port int3 ti4 0:port int2 1:to3 0:port 1:to1 0:port int1 ti0 pccr pcfc ? ? pc5 pc4 pc3 pc2 pc1 pc0 0 0 input port, int4 input port input port, int3, ti4 input port, int2 input port input port, int1, ti0 1 0 output port 1 1 to7 to5 output port to3 to1 output port 0 1 to7 to5 do not use this setting note: do not set tmp92cd54i 2009-12-26 92cd54i-54 tentative 3.5.5 port d (pd0-pd7) port d is an 8-bit general-purpose input/ output port for which each bit can be individually specified as input or output. the control register, pdcr, and function register, pdfc, are used to specify input or output. in addition to the general-purpose input/output port function, the pins can also function as 16-bit timer input/output or interrupt input. timer inputs ti8, ti9, tia, tib and external interrupts int5, int6, and int7 are always input-enabled except when in idle3 or stop mode. wakeup interrupts wuint0 to wuint7 are always input-enabled. a reset initializes port d to input port mode. figure 3.5.6 portd pd2 (to8/a18/wuint2) pd3 (to9/a19/wuint3) pd6 (toa/a22/wuint6) pd7 (tob/a23/wuint7) s 0 1 selector s 1 0 selecto r port read data s 0 1 selector timer output a ddress bus wake up request pdcr register pdfc register pd register pd0 (ti8/int5/a16/wuint0) pd1 (ti9/int6/a17/wuint1) pd4 (tia/int7/a20/wuint4) pd5 (tib/a21/wuint5) pdcr register pdfc register pd register s 0 1 selecto r s 1 0 selecto r address bus port read data wake up request interrupt request timer input tmp92cd54i 2009-12-26 92cd54i-55 tentative table 3.5.6 portd registers symbol name address 7 6 5 4 3 2 1 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 r/w 0 0 0 0 0 0 0 0 pd portd 34h input/output pd7c pd6c pd5c pd4c pd3c pd2c pd1c pd0c w 0 0 0 0 0 0 0 0 pdcr portd control register 36h (no rmw) 0:input 1:output pd7f pd6f pd5f pd4f pd3f pd2f pd1f pd0f w 0 0 0 0 0 0 0 0 pdfc portd function register 37h (no rmw) 0:port wuint 7 1:tob a23 0:port wuint 6 1:toa a22 0:port tib wuint 5 1:a21 0:port tia int7 wuint 4 1:a20 0:port wuint 3 1:to9 a19 0:port wuint 2 1:to8 a18 0:port ti9 int6 wuint 1 1:a17 0:port ti8 int5 wuint 0 1: a16 pdcr pdfc pd7 pd6 pd 5 pd4 pd3 pd2 pd1 pd0 0 0 input port, wuint7 input port, wuint6 input port, tib, wuint5 input port, int7, tia, wuint4 input port, wuint3 input port, wuint2 input port, int6, ti9, wuint1 input port, int5, ti8, wuint0 1 0 output port 1 1 tob toa, tib, wuint5 tia, int7, wuint4 to9 to8 ti9, int6, wuint1 ti8, int5, wuint0 0 1 a23 a22 a21 a20 a19 a18 a17 a16 note 1: ports d0, d1, and d4 are assigned two interrupt sources each (pd0: int5/wuint0, pd1: int6/wuint1, pd4: int7/wuint4). if both interrupt requests are issued when these interrupts are enabled, both are handled. to use only either of the two interrupt sour ces, disable (mask) the other interrupt source using the interrupt mask register or wakeup mask register. note 2: to use any pin shared with an interrupt input as an input/output port pin, ensure that interrupt requests are disabled before setting the pdfc and pdcr registers. tmp92cd54i 2009-12-26 92cd54i-56 tentative 3.5.6 port f (pf0-pf7) port f is an 8-bit general-purpose input/ output port for which each bit can be individually specified as input or output. the control register, pfcr, and function register, pffc, are used to specify input or output. in addition to the general-purpose input/output port function, the pins can also function as serial interface and contro ller area network (can) pins. serial receive data pins rxd0 and rxd1, can receive data pin rx, clear-to-send pins cts0 and cts1, and serial clock pins sc lk0 and sclk1 are always input-enabled except when in idle3 or stop mode. a reset initializes port f to input port mode. figure 3.5.7 portf (pf0, pf3 and pf6) when pfcr register is ?0? and pffc register is ?1?, txd is open drain output. s 0 1 selector s 1 0 selecto r txd out p ut port read data pf0 (txd0) pf3 (txd1) pfcr register pffc register pf register s 0 1 selector s 1 0 selector tx out p ut port read data pf6 (tx) pfcr register pffc register pf register tmp92cd54i 2009-12-26 92cd54i-57 tentative figure 3.5.8 portf (pf1, pf4, pf7, pf2 and pf5) port read data rxd input pf register s 1 0 selecto r pf1 (rxd0) pf4 (rxd1) pf7 (rx) pfcr register pffc register pf2 (sclk0/ cts0 ) pf5 (sclk1/ cts1 ) s 0 1 selector s 1 0 selecto r port read data s 0 1 selector sclk output (reserved) sclk input cts input pfcr register pffc register pf register tmp92cd54i 2009-12-26 92cd54i-58 tentative table 3.5.7 portf registers symbol name address 7 6 5 4 3 2 1 0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 r/w 0 0 0 0 0 0 0 0 pf portf 3ch input/output pf7c pf6c pf5c pf4c pf3c pf2c pf1c pf0c w 0 0 0 0 0 0 0 0 pfcr portf control register 3eh (no rmw) 0:input 1:output pf7f pf6f pf5f pf4f pf3f pf2f pf1f pf0f w 0 0 0 0 0 0 0 0 pffc portf function register 3fh (no rmw) 0:port 1:rx 0:port 1:tx 0:port cts1 1:sclk1 0:port 1:rxd1 0:port 1:txd1 0:port cts0 1:sclk0 0:port 1:rxd0 0:port 1:txd0 pfcr pffc pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 0 0 input port, rx input port input port, sclk1 (input), cts1 input port, rxd1 input port input port, sclk0 (input), cts0 input port, rxd0 input port 1 0 output port 1 1 rx tx sclk1 (output) rxd1 txd1 sclk0 (output) rxd0 txd0 0 1 rx tx don?t use this setting. rxd1 txd1 (open drain) don?t use this setting. rxd0 txd0 (open drain) tmp92cd54i 2009-12-26 92cd54i-59 tentative 3.5.7 port g (pg0-pg7) port g is an 8-bit genera l-purpose input-only port. in addition to the general-purpose input port function, the pins can also function as a/d converter input pins. a/d conversion inputs an0 to an7 are always input-enabled except when in idle3 or stop mode. figure 3.5.9 portg table 3.5.8 portg register symbol name address 7 6 5 4 3 2 1 0 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 r pg portg 40h input 3.5.8 port l (pl0-pl3) port l is an 4-bit genera l-purpose input-only port. in addition to the general-purpose input port function, the pins can also function as a/d converter input pins. a/d conversion inputs an8 to an11 are always input-enabled except when in idle3 or stop mode. figure 3.5.10 portl table 3.5.9 portl register symbol name address 7 6 5 4 3 2 1 0 ? ? ? ? pl3 pl2 pl1 pl0 r pl portl 54h ? ? ? ? input portl pl0 to pl3 (an8 to an11) port read data ad converter input portg pg0 to pg7 (an0 to an7) port read data ad converter input tmp92cd54i 2009-12-26 92cd54i-60 tentative 3.5.9 port m (pm0-pm4) port m is an 5-bit general-purpose input/ output port for which each bit can be individually specified as input or output. the control register, pmcr, and function register, pmfc, are used to specify input or output. in addition to the general-purpose input/output port function, the pins can also function as serial general-purpose in terface input/output pins. the slave select pin ss, seri al data transmit/receive pins mosi and miso, sei clock pin seclk, and sbi clock input/output (sio) pin sck2 are always input-enabled except when in idle3 or stop mode. a reset initializes port m to input port mode. figure 3.5.11 portm (pm0 to pm3) s 0 1 selector s 1 0 selecto r address bus port read data pm0 ( ss /a8) ss input pmcr register pmfc register pm register when pmode register is ?1?, pm1 to pm3 signals are open drain output. pm1 (mosi/a9) pm2 (miso/a10) pm3 (seclk/a11) s 0 1 selector s 1 0 selecto r port read data s 0 1 selector address bus mosi input miso input seclk input mosi, miso, seclk output enable sei monito r mosi output miso output seclk output pmcr register pmfc register pm register tmp92cd54i 2009-12-26 92cd54i-61 tentative figure 3.5.12 portm (pm4) table 3.5.10 portm register symbol name address 7 6 5 4 3 2 1 0 ? ? ? pm4 pm3 pm2 pm1 pm0 r/w ? ? ? 0 0 0 0 0 pm portm 58h input/output ? ? ? ? odem3 odem2 odem1 - r/w ? ? ? ? 0 0 0 - pmode portm open drain enable register 59h p m 3 output 0:cmos 1:open drain pm2 output 0:cmos 1:open drain pm1 output 0:cmos 1:open drain ? ? ? pm4c pm3c pm2c pm1c pm0c w ? ? ? 0 0 0 0 0 pmcr portm control register 5ah (no rmw) 0:input 1:output ? ? ? pm4f pm3f pm2f pm1f pm0f w ? ? ? 0 0 0 0 0 pmfc portm function register 5bh (no rmw) 0:port 1:sck2 0:port 1: seclk a11 0:port 1:miso a10 0:port 1:mosi a9 0:port 1: ss a8 pmcr pmfc ? ? ? pm4 pm3 pm2 pm1 pm0 0 0 ? ? ? input port, sck2 (input) input port input port input port input port, ss 1 0 ? ? ? output port 1 1 ? ? ? sck2 (output) seclk miso mosi ss 0 1 ? ? ? don?t use this setting a11 a10 a9 a8 s 0 1 selector s 1 0 selecto r port read data s 0 1 selector sck output (reserved) sck input pm4 (sck2) pmcr register pmfc register pm register tmp92cd54i 2009-12-26 92cd54i-62 tentative 3.5.10 port n (pn0-pn6) port n is an 7-bit general-purpose input/ output port for which each bit can be individually specified as input or output. the control register, pncr, and function register, pnfc, are used to specify input or output. in addition to the general-purpose input/output port function, the pins can also function as serial channel input/output pins. the sbi clock input/output (sio) pins sck0 and sck1, sbi data input (sio) pins si0 and si1, sbi clock input/output (i2c) pins scl0 and scl1, and sbi data input/output (i2c) pins sda0 and sda1 are always inpu t-enabled except when in idle3 or stop mode. a reset initializes port n to input port mode. figure 3.5.13 portn pn0 (sck0) pn3 (sck1/a12) s 0 1 selector s 1 0 selecto r port read data s 0 1 selector sck output address bus sck input pncr register pnfc register pn register pn1 (so0/sda0) pn2 (si0/scl0) pn4 (so1/sda1/a13) pn5 (si1/scl1/a14) pn6 (so2/sda2/a15) pncr register pnfc register pn register s 0 1 selector s 1 0 selecto r p o r t r ead data s 0 1 selector so/sda output scl output address bus sda input si/scl input when pnode register is ?1?, pn1, pn2, pn4, pn5 and pn6 signals are open drain output. tmp92cd54i 2009-12-26 92cd54i-63 tentative table 3.5.11 portn register symbol name address 7 6 5 4 3 2 1 0 ? pn6 pn5 pn4 pn3 pn2 pn1 pn0 r/w ? 0 0 0 0 0 0 0 pn portn 5ch input/output ode72 oden6 oden5 oden4 ? oden2 oden1 ? r/w r/w 0 0 0 0 ? 0 0 ? pnode portn open drain enable register 5dh p72 output 0:cmos 1:open drain pn6 output 0:cmos 1:open drain pn5 output 0:cmos 1:open drain pn4 output 0:cmos 1:open drain pn2 output 0:cmos 1:open drain pn1 output 0:cmos 1:open drain ? pn6c pn5c pn4c pn3c pn2c pn1c pn0c w ? 0 0 0 0 0 0 0 pncr portn control register 5eh (no rmw) 0:input 1:output ? pn6f pn5f pn4f pn3f pn2f pn1f pn0f w ? 0 0 0 0 0 0 0 pnfc portn function register 5fh (no rmw) 0:port 1: so2 sda2 a15 0:port si1 1:scl1 a14 0:port 1:so1 sda1 a13 0:port 1:sck1 a12 0:port si0 1:scl0 0:port 1:so0 sda0 0:port 1:sck0 pncr pnfc ? pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 0 ? input port input port input port input port, sck1 (input) input port, si0 input port input port, sck0 (input) 1 0 ? output port 1 1 ? so2/sda 2 scl1 so1/sda 1 sck1 (output) scl0 so0/sda 0 sck0 (output) 0 1 ? a15 a14 a13 a12 don?t use this setting. tmp92cd54i 2009-12-26 92cd54i-64 tentative 3.6 memory controller 3.6.1 overview of functions the tmp92cd54i memory cont roller can control a block address space as follows: (1) accessing a block address space in an external area the memory controller can specify a block size and start addre ss for a single block address space allocated in an external area. (2) specifying a memory type the memory controller can specify either sram or rom as the type of memory to be connected to a block address space. (3) specifying a data bus width the data bus width of a block address space is fixed to eight bits. (4) controlling wait states the memory controller can control the number of wait states for exte rnal bus cycles using the wait specification bit in a control register and the wait input pin. it can specify the number of wait states separately for a read cycle and write cycle. the memory controller supports the following five modes to control the number of wait states: 0 wait states, 1 wait state, 2 wait states, 3 wait states, n wait states (controlled using the wait pin) 3.6.2 control registers and operation upon a reset this section describes the register s used to control the memory controller as well as the status upon a reset and ne cessary settings. (1) control registers the following control registers are used for the memory controller: (2) operation upon a reset upon a reset, the block address space is set to addresses 000000h to ffffefh. after a reset has been released, use the memo ry start address regist er (msar) and memory address mask register (mamr) to specify the block address space and configure the control register (bcsl/h). to make the settings effective, set bcsl tmp92cd54i 2009-12-26 92cd54i-65 tentative 3.6.3 basic functions and register settings this section describes the memory controller functions for setting the block address area, memory type, and number of wait states. (1) specifying the block address space clearing bcsh tmp92cd54i 2009-12-26 92cd54i-66 tentative (i) setting the memory st art address register bits ms23 to ms16 in the memory start address register corres pond to address bits a23 to a16, respectively. the start lower address, a15 to a0, are always 0000h. the start address of the block address space can, therefore, be specified within the range from 000000h to ff0000h, in 64-kbyte units. (ii) setting the memory ad dress mask register the memory address mask register specifies whether each bit in the address will be compared or not. the bits cleared to 0 will be compared while those set to 1 will not be compared. bit a23 is always compared. the address bits for the block address space that can be masked are a22 to a15. the following sizes can be specif ied for the block address space: table 3.6.1 block address space size (bytes) cs area 256 512 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m cs note: upon a reset, bcsh tmp92cd54i 2009-12-26 92cd54i-67 tentative (iv) if the block overlaps built-in memory space if the specified block address space overlaps the built-in memory space, the block address space will be handled according to the following order of priority: this means that priorities are assigned to prevent collision rather than remapping the block addresses. if any address outside the specified block address space is accessed, the number of wait bus cycles is set to 1 (with the rd and wr signals output but the cs signal not output). it is a fixed parameter. (2) controlling wait states an external bus cycle is completed in two states (100 ns at 20 mhz) at a minimum. the number of wait states for read and write cycles can be specified by setting tmp92cd54i 2009-12-26 92cd54i-68 tentative (3) bus access timing ? external read/write bus cycle (0 wait states) ? external read/write bus cycle (1 wait state) figure 3.6.2 external read/write bus cycle (0 and 1 wait status) t1 t2 in p ut output read write address cs rd d7 to 0 wr d7 to 0 clk (20mhz) t1 tw in p ut output t2 read write address cs rd d7 to 0 wr d7 to 0 clk (20mhz) tmp92cd54i 2009-12-26 92cd54i-69 tentative ? external read/write bus cycle (0 wait states in wait pin input mode) ? external read/write bus cycle (n wait states in wait pin input mode) figure 3.6.3 external read/write bus cycle ( wait pin input mode) t1 t2 in p ut output read write sampling address cs rd d7 to 0 wr d7 to 0 clk (20mhz) wait t1 tw in p ut output read write sampling t2 sampling address cs rd d7 to 0 wr d7 to 0 clk (20mhz) wait tmp92cd54i 2009-12-26 92cd54i-70 tentative ? example wait input circuit (for 5 wait states) figure 3.6.4 example wait input circuit (for 5 wait status) d q ck res d q ck res dq ck res dq ck res dq ck res wait ff0 ff1 ff2 ff3 ff4 clk cs rd wr ff2 q ff0 d ff0 q ff1 q ff_res ff3 q 12 3 4567 cs rd clk (20mhz) wait tmp92cd54i 2009-12-26 92cd54i-71 tentative 3.6.4 registers this section summarizes the memory control regi sters and their settings. for the address of each register, refer to chapter 5, "list of special function registers." (1) control registers the memory is controlled with the bcsl and bcsh registers. block cs/wait control register (l) 7 6 5 4 3 2 1 0 bit symbol ? bww2 bww1 bww0 ? bw r2 bwr1 bwr0 read/w rite w af ter r eset ? 0 1 0 ? 0 1 0 tmp92cd54i 2009-12-26 92cd54i-72 tentative (2) block address space specification registers the start address and range of the block address space are specified using two registers, memory start address register (msar) and memory a ddress mask register (mamr). memory start address register 7 6 5 4 3 2 1 0 bit symbol ms23 ms22 ms21 ms20 ms19 ms18 ms17 ms16 read/w rite r/w af ter r eset 1 1 1 1 1 1 1 1 tmp92cd54i 2009-12-26 92cd54i-73 tentative 3.7 8-bit timers the tmp92cd54i contains eight channels of 8-bit timers (timers 0 to 7). the timers are grouped into four modules, each consisting of two channels (timer 01, timer 23, timer 45 and timer 67) and can operate in one of the following four modes: ? 8-bit interval timer mode ? 16-bit interval timer mode ? 8-bit programmable square wave (ppg, with va riable cycle and duty ratio) output mode ? 8-bit pulse width modulation (pwm, with fixed cycle and variable duty ratio) output mode figure 3.7.1 to figure 3.7.4 show bloc k diagrams of timers 01, 23, 45 and 67. each channel consists of an 8-bit up-counter , 8-bit comparator and 8-bit timer register. a timer flip-flop and prescaler are provided for each pair of two channels. the timer operating mode and flip-flop are controlled using five special function registers (sfr). four modules (timers 01, 23, 45 and 67) operat e independently of each other. all modules operate in the same way except the differences in specification listed in table 3.7.1. this section only describes the operation of timer 01. table 3.7.1 registers and pins for each module module specification timers 01 timers 23 timers 45 timers 67 input pin for external clock ti0 (shared with pc0) - ti4 (shared with pc3) - external pin output pin for timer flip-flop to1 (shared with pc1) to3 (shared with pc2) to5 (shared with pc4) to7 (shared with pc5) timer run register trun01 (0080h) trun23 (0088h) trun45 (0090h) trun67 (0098h) timer register treg0 (0082h) treg1 (0083h) treg2 (008ah) treg3 (008bh) treg4 (0092h) treg5 (0093h) treg6 (009ah) treg7 (009bh) timer mode register tmod01 (0084h) tmod23 ( 008ch) tmod45 (0094h) tmod67 (009ch) sfr (address) timer flip-flop control register tffcr1 (0085h) tffcr3 (008dh) tffcr5 (0095h) tffcr7 (009dh) tmp92cd54i 2009-12-26 92cd54i-74 tentative 3.7.1 block diagram for each module figure 3.7.1 timers 01 block diagram timer 1 interrupt output: intt1 match detect run/clear prescale r clock: t0 t0trg external input clock: ti0 tmod01 tmp92cd54i 2009-12-26 92cd54i-75 tentative figure 3.7.2 timers 23 block diagram timer 3 interrupt output: intt3 match detect run/clear prescale r clock: t0 t2trg tmod23 tmp92cd54i 2009-12-26 92cd54i-76 tentative figure 3.7.3 timers 45 block diagram timer 5 interrupt output: intt5 match detect run/clear prescaler clock: t0 t4trg external input clock: ti4 tmod45 tmp92cd54i 2009-12-26 92cd54i-77 tentative figure 3.7.4 timers 67 block diagram timer 1 interrup7 output: intt7 match detect run/clear prescaler clock: t0 t6trg tmod67 tmp92cd54i 2009-12-26 92cd54i-78 tentative 3.7.2 description of each circuit (1) prescaler the 9-bit prescaler divides the 1/4 cpu cloc k (fc/4) to generate the input clock for timer 01. the operation of the prescaler can be controlled using trun01 tmp92cd54i 2009-12-26 92cd54i-79 tentative (2) up-counters (uc0 and uc1) the up-counters are 8-bit binary counters that increment the count according to the input clock specified with the timer mode register, tmod01. the input clock for uc0 is selected from among an external clock supplied through the ti0 pin and three types of prescaler output clock, t1, t4 and t16, according to the setting of tmod01 tmp92cd54i 2009-12-26 92cd54i-80 tentative (3) timer registers (treg0 and treg1) a timer register is an 8-bit register that sp ecifies an interval time. if the up-counter value matches the value set in the timer register, the comparator match detection signal is activated. if the timer register is set to 00h, the match signal is activated when the up-counter overflows. treg0 is paired with a register buffer to form a double-buffer configuration. the double buffer is controlled using trun01 tmp92cd54i 2009-12-26 92cd54i-81 tentative (4) comparator (cp0) the comparator compares the up-counter value with the value set in the timer register and, if they match, clears the up-counter to 0 and issues an interrupt (intt0-1). it also inverts the value of the timer flip-flop if inversion is enabled. (5) timer flip-flop (tff1) the timer flip-flop (tff1) is inverted wi th a match detection signal from the comparator. the timer flip-flop contro l register, tffcr1 tmp92cd54i 2009-12-26 92cd54i-82 tentative 3.7.3 8-bit timer registers timers 01 operating control register 7 6 5 4 3 2 1 0 bit symbol t0rde - - - i2t01 t01prun t1run t0run read/write r/w r/w after reset 0 - - - 0 0 0 0 function double buffer 0: disable 1: enable idle2 0: stop 1: operate timer run/stop control 0: stop & clear 1: run (count up) 0 stop & clear 1 run (count up) trun01 (0080h) timer run/stop control treg0 double buffer control 0 disable 1 enable i2t01: operation in idle2 mode (for details, see "3.3.2 standby controller") t01prun: prescaler operation t1run: timer 1 operation t0run: timer 0 operation note1: trun01 bits 4 to 6 return undefined values if read. note2: in ppg/pwm mode, tmp92cd54i 2009-12-26 92cd54i-83 tentative timer 45 operation control register 7 6 5 4 3 2 1 0 bit symbol t4rde - - - i2t45 t45prun t5run t4run read/write r/w r/w after reset 0 - - - 0 0 0 0 function double buffer 0: disable 1: enable idle2 0: stop 1: operate timer run/stop control 0: stop & clear 1: run (count up) trun45 (0090h) timer run/stop control 0 stop & clear 1 run (count up) treg4 double buffer control 0 disable 1 enable i2t45: operation in idle2 mode (for details, see "3.3.2 standby controller") t45prun: prescaler operation t5run: timer 5 operation t4run: timer 4 operation note1: trun45 bits 4 to 6 return undefined values if read. note2: in ppg/pwm mode, tmp92cd54i 2009-12-26 92cd54i-84 tentative timer 01 mode register 7 6 5 4 3 2 1 0 bit symbol t01m1 t01m0 pwm01 pwm00 t1clk1 t1clk0 t0clk1 t0clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for timer 1 00: t0trg 01: t1 10: t16 11: t256 source clock for timer 0 00: ti0 pin (note) 01: t1 10: t4 11: t16 00 ti0 (external input) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) tmod01 tmp92cd54i 2009-12-26 92cd54i-85 tentative timer 23 mode register 7 6 5 4 3 2 1 0 bit symbol t23m1 t23m0 pwm21 pwm20 t3clk1 t3clk0 t2clk1 t2clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for timer 3 00: t2trg 01: t1 10: t16 11: t256 source clock for timer 2 00: reserved 01: t1 10: t4 11: t16 00 do not set 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) tmod23 tmp92cd54i 2009-12-26 92cd54i-86 tentative timer 45 mode register 7 6 5 4 3 2 1 0 bit symbol t45m1 t45m0 pwm41 pwm40 t5clk1 t5clk0 t4clk1 t4clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for timer 5 00: t4trg 01: t1 10: t16 11: t256 source clock for timer 4 00: ti4 pin (note) 01: t1 10: t4 11: t16 00 ti4 (external input) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) tmod45 tmp92cd54i 2009-12-26 92cd54i-87 tentative timer 67 mode register 7 6 5 4 3 2 1 0 bit symbol t67m1 t67m0 pwm61 pwm60 t7clk1 t7clk0 t6clk1 t6clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for timer 7 00: t6trg 01: t1 10: t16 11: t256 source clock for timer6 00: reserved 01: t1 10: t4 11: t16 00 do not set 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) tmod67 tmp92cd54i 2009-12-26 92cd54i-88 tentative timer 1 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol - - - - tff1c1 tff1c0 tff1ie tff1is read/write r/w after reset - - - - 1 1 0 0 function 00: invert tff1 01: set tff1 10: clear tff1 11: don?t care tff1 control for inversion 0: disable 1: enable tff1 inversion select 0: timer 0 1: timer 1 0 inversion by timer 0 1 inversion by timer 1 0 disabled 1 enabled 00 inverts the value of tff1 01 sets tff1 to 1 10 clears tff1 to 0 11 don?t care control of tff1 tffcr1 (0085h) inverse signal for timer flop-flop 1 (tff1) (don?t care except in 8-bit timer mode) inversion of tff1 note: tffcr1 bits 4 to 7 return undefined values if read. read- modify- write not allowed figure 3.7.13 register for 8-bit timers (tffcr1) tmp92cd54i 2009-12-26 92cd54i-89 tentative timer 3 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol - - - - tff3c1 tff3c0 tff3ie tff3is read/write r/w after reset - - - - 1 1 0 0 function 00: invert tff3 01: set tff3 10: clear tff3 11: don?t care tff3 control for inversion 0: disable 1: enable tff3 inversion select 0: timer 2 1: timer 3 0 inversion by timer 2 1 inversion by timer 3 0 disabled 1 enabled 00 inverts the value of tff3 01 sets tff3 to 1 10 clears tff3 to 0 11 don?t care control of tff3 tffcr3 (008dh) inverse signal for timer flip-flop 3 (tff3) (don?t care except in 8-bit timer mode) inversion of tff3 note: tffcr3 bits 4 to 7 return undefined values if read. read- modify- write not allowed figure 3.7.14 register for 8-bit timers (tffcr3) tmp92cd54i 2009-12-26 92cd54i-90 tentative timer 5 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol - - - - tff5c1 tff5c0 tff5ie tff5is read/write r/w after reset - - - - 1 1 0 0 function 00: invert tff5 01: set tff5 10: clear tff5 11: don?t care tff5 control for inversion 0: disable 1: enable tff5 inversion select 0: timer 4 1: timer 5 0 inversion by timer 4 1 inversion by timer 5 0 disabled 1 enabled 00 inverts the value tff5 01 sets tff5 to 1 10 clears tff5 to 0 11 don?t care control of tff5 tffcr5 (0095h) inverse signal for timer flip-flop 5 (tff5) (don?t care except in 8-bit timer mode) inversion of tff5 note: tffcr5 bits 4 to 7 return undefined values if read. read- modify- write not allowed figure 3.7.15 register for 8-bit timers (tffcr5) tmp92cd54i 2009-12-26 92cd54i-91 tentative timer 7 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol - - - - tff7c1 tff7c0 tff7ie tff7is read/write r/w after reset - - - - 1 1 0 0 function 00: invert tff7 01: set tff7 10: clear tff7 11: don?t care tff7 control for invertsion 0: disable 1: enable tff7 inversion select 0: timer 6 1: timer 7 0 inversion by timer 6 1 inversion by timer 7 0 disabled 1 enabled 00 inverts the value of tff7 01 sets tff7 to 1 10 clears tff7 to 0 11 don?t care control of tff7 tffcr7 (009dh) inverse signal for timer flip-flop 7 (tff7) (don?t care except in 8-bit timer mode) inversion of tff7 note: tffcr7 bits 4 to 7 return undefined values if read. read- modify- write not allowed figure 3.7.16 register for 8-bit timers (tffcr7) tmp92cd54i 2009-12-26 92cd54i-92 tentative timer registers (treg 0 to 7) symbol address 7 6 5 4 3 2 1 0 - w treg0 82h (no rmw) undefined - w treg1 83h (no rmw) undefined - w treg2 8ah (no rmw) undefined - w treg3 8bh (no rmw) undefined - w treg4 92h (no rmw) undefined - w treg5 93h (no rmw) undefined - w treg6 9ah (no rmw) undefined - w treg7 9bh (no rmw) undefined note: the treg registers are used for the comparator. a match between uc and treg causes a match detection signal to be generated. see examples in "3.7.4 operation in each mode." figure 3.7.17 register for 8-bit timers (treg0~treg7) tmp92cd54i 2009-12-26 92cd54i-93 tentative 3.7.4 operation in each mode (1) 8-bit timer mode each of timers 0 and 1 can be used as an independent 8-bit interval timer. a. generating interrupts at regu lar intervals (u sing timer 1) to use timer 1 to generate timer 1 interrupts (intt1) at regular intervals, first stop timer 1 and then set the operating mode, input clock and interval in tmod01 and treg1. next, enable intt1 and then start counting with timer 1. example: to generate intt1 interrupts every 40 s when fc = 20 mhz, set the registers in the following order: msb lsb 7 6 5 4 3210 trun01 ? x x x ??0? stop timer 1 and clear it to zero. tmod01 0 0 x x 01-- select 8-bit timer mode and set the input clock to t1 (0.4- s resolution, at fc = 20 mhz). treg1 0 1 1 0 0100 set treg1 to 40 s t1 = 100 = 64h. intet01 x 1 0 1 ???? enable intt1 and set the interrupt level to 5. trun01 ? x x x ?11? start counting with timer 1. x = don't care " ? " = no change see table 3.7.3 for how to select the input clock. table 3.7.3 selecting interrupt interval and the input clock using 8-bit timer input clock interrupt interval (at fc = 20 mhz) resolution t1 (8/fc) t4 (32/fc) t16 (128/fc) t256 (2048/fc) 0.4 s to 102.4 s 1.6 s to 409.6 s 6.4 s to 1.639 ms 102.4 s to 26.22 ms 0.4 s 1.6 s 6.4 s 102.4 s note: the available input clocks for timer 0 and timer 1 differ as follows: timer 0: timer 0 input (ti0), t1, t4, or t16 timer 1: timer 0 match detection signal (t0trg), t1, t16, or t256 uc1 & treg1 match detect intt1 interru p t re q uest occu r treg1 = 64h = 40 s t1 tmp92cd54i 2009-12-26 92cd54i-94 tentative b. outputting a square wave of 50% duty ratio invert the value of the timer flip-flop ( tff1) at regular intervals and output the inverted value to the timer flip-flop output pin (to1). example: to output a square wave having a period of 2.4 s when fc = 20 mhz, set the registers in the following order. either timer 0 or timer 1 can be used for that purpose. the example uses timer 1. 7 6 5 4 3210 trun01 ? x x x ??0? stop timer 1 and clear it to zero. tmod01 0 0 x x 01?? select 8-bit timer mode and set the input clock to t1 (0.4 s, at fc = 20 mhz). treg1 0 0 0 0 0011 set treg1 to 2.4 s t1 2 = 3. tffcr1 x x x x 1011 clear tff1 to 0 and set it to be inverted with a match detection signal from timer 1. pccr x x ? ? ??1? pcfc x x ? ? -?1- set pc1 to the to1 output pin. trun01 ? x x x ?11? start counting with timer 1. x = don't care " ? " = no change 0.77 s at @fc = 20 bit7 2 t1 intt1 uc1 clea r tff1 bit 0 bit 1 trun01 tmp92cd54i 2009-12-26 92cd54i-95 tentative c. incrementing the timer 1 count with a match output from timer 0 select 8-bit timer mode and set the input cl ock for timer 1 to the timer 0 comparator output. figure 3.7.19 timer 1 count up on signal from timer 0 (2) 16-bit timer mode a pair of timers 0 and 1 can be used as a 16-bit interval timer. setting tmod01 tmp92cd54i 2009-12-26 92cd54i-96 tentative example: to generate intt1 interrupts every 0.4 se cond when fc = 20 mhz, set the following values in timer registers treg0 and treg1: if t16 (6.4 s at 20 mhz) is counted as the input clock: 0.4 s 6.4 s = 62500 = f424h therefore, set treg0 = 24h and treg1 = f4h. the timer 0 comparator outputs a match dete ction signal every time up-counter uc0 matches treg0 but uc0 is not cleared at that time. the timer 1 comparator outputs a match detection signal at every comparison timing where up-counter uc1 matches treg1. if bo th timers 0 and 1 output match detection signals simultaneously, up-c ounters uc0 and uc1 are cleared to zero and an intt1 interrupt occurs. the value of timer flip-flop tff1 is also inverted if inversion is enabled. example: when treg1 = 04h and treg0 = 80h: figure 3.7.21 timer output by 16-bit interval timer mode (3) 8-bit ppg (programmable square wave) output mode timer 0 can be used to output a square wave having any specified frequency and duty ratio. either low-active or high-active output pulses can be selected. in this mode, timer 1 is disabled. the square wave is ou tput through to1 (shared with pc1). figure 3.7.22 8 bit ppg output waveforms 0080h 0180h 0280h 0380h 0480h value of up-counter(uc1, uc0): uc0 & treg0 match detect signal 0000h inversion interrupt intt1 timer output to1 uc1 & treg1 match detect signal t t h t l treg0 and uc0 match (interrupt intt0) treg0 treg1 treg1 and uc0 match ( interru p ut intt1 ) to1 dut y c y cle period tmp92cd54i 2009-12-26 92cd54i-97 tentative in this mode, 8-bit up-counter uc0 inverts the timer output every time its value matches the value in timer register treg0 or treg1 to output a programmable square wave. the value of treg0 must be smaller than that of treg1. in this mode, the up-counter for timer 1, uc1, cannot be used. timer 1 must, however, be set to the counting st ate by setting trun01 tmp92cd54i 2009-12-26 92cd54i-98 tentative example: outputting pulses having a duty rati o of 1/4 at 62.5 khz (when fc = 20 mhz) 16 s calculate the value to set in the timer register, as follows: to obtain a frequency of 62.5 khz, create a waveform having a period of t = 1/62.5 khz = 16 s. t1 = 0.4 s (at 20 mhz): 16 s 0.4 s = 40 therefore, treg1 = 40 = 28h. next, to obtain a duty ratio of 1/4, using t x 1/4 = 16 s x 1/4 = 4 s: 4 s 0.4 s = 10 therefore, treg0 = 10 = 0ah. 7 6 5 4 3210 trun01 0 x x x ?000 stop timers 0 and 1 and clear them to zero. tmod01 1 0 x x xx01 select 8-bit ppg mode and set the input clock to t1. treg0 0 0 0 0 1010 write 0ah. treg1 0 0 1 0 1000 write 28h. tffcr1 x x x x 011x set tff1 and enable inversion. setting 10 results in a negative-logic output waveform. pccr x x ? ? ??1? pcfc x x ? ? -?1- set pc1 to the to1 pin. trun01 1 x x x ?111 enable double buffer and start counting with timers 0 and 1. x = don't care " ? " = no change tmp92cd54i 2009-12-26 92cd54i-99 tentative (4) 8-bit pwm output mode this mode is supported only for timer 0. in this mode, a pwm signal having a resolution of up to eight bits can be ou tput. the pwm signal is output through to1 (shared with pc1). in this mode, timer 1 can be output as an 8-bit timer. the timer output is inverted when the up-counter (uc0) value matches the value set in the timer register (treg0) or when the 2 n counter overflows (n = 6, 7 or 8, as specified with tmod01 tmp92cd54i 2009-12-26 92cd54i-100 tentative in this mode, if the double buffer for treg0 is enabled, the value of the register buffer is shifted into treg0 when an 2 n overflow is detected. using the double buffer facilitates pr ocessing for a small duty ratio. q 2 up-counter = q 2 up-counter = q 1 q 1 q 2 q 3 shift into treg0 match with treg0 2 n overflo w treg0 (value to be compared) register buffe r treg0 (register buffer) write figure 3.7.27 register buffer operation example: using timer 0 to output the following pwm waveform through the to1 pin (fc = 20 mhz) 36.0 s 51.2 s to obtain a pwm period of 51.2 s with t1 = 0.4 s (at fc = 20 mhz): 51.2 s 0.4 s = 2 n = 128 therefore, set n to 7. since the low-level period is 36.0 s, set treg0 to the following value when t1 = 0.4 s: 36.0 s 0.4 s = 90 = 5ah msb lsb 7 6 5 4 3210 trun01 ? x x x ???0 stop timer 0 and clear it to zero. tmod01 1 1 1 0 ??01 select 8-bit pwm mode (period = 2 7 ) and set the input clock to ? 1. treg0 0 1 0 1 1010 write 5ah. tffcr1 x x x x 101x clear tff1 and enable inversion. pccr x x ? ? ??1? pcfc x x ? ? -?1- set pc1 to the to1 pin. trun01 1 x x x ?1-1 enable double buffer and start counting with timer 0. x = don't care " ? " = no change tmp92cd54i 2009-12-26 92cd54i-101 tentative table 3.7.4 pwm cycle pwm interval (at fc = 20mhz) t1 t4 t16 2 6 25.6 s ( 39.06 khz ) 102.4 s ( 9.77 khz ) 409.6 s ( 2.44 khz ) 2 7 51.3 s ( 19.53 khz ) 204.8 s ( 4.88 khz ) 819.2 s ( 1.22 khz ) 2 8 102.4 s ( 9.77 khz ) 409.6 s ( 2.44 khz ) 1.6384 ms ( 0.61 khz ) (5) settings for each timer mode table 3.7.5 shows the sfr settings for each mode. table 3.7.5 interval timer mode setting registers register name tmod01 tffcr1 tmp92cd54i 2009-12-26 92cd54i-102 tentative 3.8 16-bit timers/event counters the tmp92cd54i contains two channels of 16- bit timers/event counters (timer 8 and timer a), which can operate in the following modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable square wave (ppg) output mode the following operating modes are also supported by using the capture function: ? frequency measurement mode ? pulse width measurement mode ? time difference measurement mode figure 3.8.1 and figure 3.8.2 show block diagrams of timers 8 and a. each channel mainly consists of a 16-bit up-counter, two 16-bit timer registers (one with double-buffer configurat ion), two 16-bit capture registers, two comparators, a capture input controller, timer flip-flops and their controller. each timer is controlled with 11 register (sfr) bytes. the two channels, timer 8 and timer a, operate independently of each other. both channels operate in the same way except the differences in specification listed in table 3.8.1. this section only describes the operation of timer 8. table 3.8.1 differences between timer 8 and timer a channel specification timer 8 timer a ti8 (also used as pd0) tia (also used as pd4) external clock / capture trigger input pins ti9 (also used as pd1) tib (also used as pd5) to8 (also used as pd2) toa (also used as pd6) external pins timer flip-flop output pins to9 (also used as pd3) tob (also used as pd7) timer run register trun8 (00a0h) truna (00b0h) timer mode register tmod8 (00a2h) tmoda (00b2h) timer flip-flop control register tffcr8 (00a3h) tffcra (00b3h) treg8l (00a8h) tregal (00b8h) treg8h (00a9h) tregah (00b9h) treg9l (00aah) tregbl (00bah) timer register treg9h (00abh) tregbh (00bbh) cap8l (00ach) capal (00bch) cap8h (00adh) capah (00bdh) cap9l (00aeh) capbl (00beh) sfr (address) capture register cap9h (00afh) capbh (00bfh) tmp92cd54i 2009-12-26 92cd54i-103 tentative 3.8.1 block diagram intenal data bus internal data bus run/ clear match detection 16-bit comparator (cp8) 16-bit up counter (uc8) 16-bit time register treg9h/l match detection count clock tmod8 tmp92cd54i 2009-12-26 92cd54i-104 tentative intenal data bus internal data bus run/ clear match detection 16-bit comparator (cpa) 16-bit up-counter (uca) 16-bit time register tregbh/l match detection count clock tmoda tmp92cd54i 2009-12-26 92cd54i-105 tentative 3.8.2 operation of each circuit (1) prescaler a 5-bit prescaler provides a clock source for timer 8. the input clock for the prescaler, t0, is obtained by dividing fc by four. the trun8 tmp92cd54i 2009-12-26 92cd54i-106 tentative (3) timer registers (treg8h/l and treg9h/l) these two 16-bit registers are used to frequencies specify a comparator match detection signal is output if the value in up-counter uc8 matches that in the timer register. to set data in 16-bit timer registers treg8h/l and treg9h/l, use a 2-byte data transfer instruction or use two 1-byte data transfer instructions to set the lower eight bits and then the upper eight bits. the treg8 timer register ha s a double-buffer configurat ion and is paired with register buffer 8. the double buffer can be enabled or disabled using the timer 8 control register. the double buffer is disabled if the register bit is set to 0 and enabled if it is set to 1. when the double buffer is enabled, a data transfer from the register buffer to the timer register takes place if the value in the up-counter (uc8) matches the value in the timer register (treg9). upon a reset, the values in treg8 an d treg9 are undefined. to use the 16-bit timer, therefore, it is necessary to first write data to the registers. upon a reset, trun8 tmp92cd54i 2009-12-26 92cd54i-107 tentative (4) capture registers (cap8h/l and cap9h/l) the capture registers are 16-bit registers that latch the value of uc8. to read data from a capture register, use a 2-byte data transfer instruction or use two 1-byte data transfer instructions to read the lower eight bits and then the upper eight bits. the capture registers are located at the following addresses: upper 8 bits lower 8 bits cap8 0000adh 0000ach upper 8 bits lower 8 bits cap9 0000afh 0000aeh timer 8 upper 8 bits lower 8 bits capa 0000bdh 0000bch upper 8 bits lower 8 bits capb 0000bfh 0000beh timer a the capture registers are read-only. they cannot be written using a program. figure 3.8.4 address of cature registers (5) capture input and external interrupt control this circuit controls the timing for latching the value of up-counter uc8 into capture register cap8 and the generation external interrupt int5. the tmod8 |